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MPC2605ZP83 PDF预览

MPC2605ZP83

更新时间: 2024-10-29 21:04:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
36页 718K
描述
32KX72 CACHE TAG SRAM, 8ns, PBGA241, PLASTIC, BGA-241

MPC2605ZP83 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA, BGA241,19X19,50针数:241
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.5
最长访问时间:8 ns其他特性:8K X 18 TAG
JESD-30 代码:S-PBGA-B241JESD-609代码:e0
长度:25 mm内存密度:2359296 bit
内存集成电路类型:CACHE TAG SRAM内存宽度:72
功能数量:1端子数量:241
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX72
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA241,19X19,50封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
座面最大高度:2.05 mm子类别:SRAMs
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:25 mmBase Number Matches:1

MPC2605ZP83 数据手册

 浏览型号MPC2605ZP83的Datasheet PDF文件第2页浏览型号MPC2605ZP83的Datasheet PDF文件第3页浏览型号MPC2605ZP83的Datasheet PDF文件第4页浏览型号MPC2605ZP83的Datasheet PDF文件第5页浏览型号MPC2605ZP83的Datasheet PDF文件第6页浏览型号MPC2605ZP83的Datasheet PDF文件第7页 
MPC2605/D  
Rev. 12, 11/2002  
Integrated Secondary Cache  
for Microprocessors That  
Implement PowerPC  
Architecture  
The MPC2605 is a single chip, 256KB integrated look-aside  
cache with copy-back capability designed for applications  
using a 60x bus. Using 0.38 µm technology along with  
standard cell logic technology, the MPC2605 integrates data,  
tag, host interface, and least recently used (LRU) memory  
with a cache controller to provide a 256KB, 512KB, or 1MB  
Level 2 cache with one, two, or four chips on a 64-bit 60x  
bus.  
E  
ZP PACKAGE  
PBGA  
0  
CASE 1138-01  
• Single Chip L2 Cache  
• 66 or 83 MHz Zero Wait State Performance (2-1-1-1 Burst)  
• Four-Way Set Associative Cache Design  
• 32K x 72 Data Memory Array  
• 8K x 18 Tag Array  
• Address Parity Support  
• LRU Cache Control Logic  
• Copy-Back or Write-Through Modes of Operation  
• Copy-Back Buffer for Improved Performance  
• Single 3.3 V Power Supply  
• 5 V Tolerant I/O  
• One-, Two-, or Four-Chip Cache Solution (256KB, 512KB, or 1MB)  
• Single Clock Operation  
• Compliant with IEEE Standard 1149.1 Test Access Port (JTAG)  
• Supports up to Four Processors in a Shared Cache Configuration  
• High Board Density 25 mm 241 PBGA Package  

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