Datasheet > MN101EF02K

MN101EF02K

更新时间： 2024-11-14 22:09:43

品牌	Logo	应用领域
松下 - PANASONIC		/
页数	文件大小	规格书
3页	337K
描述
MN101E02H

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中文翻译

获取价格

数据手册

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MN101EF02K 数据手册

MN101E02H

Type

MN101E02H

MN101EF02K

Internal ROM type

ROM (byte)

Mask ROM

FLASH

160K

16K

RAM (byte)

Package (Lead-free)

QFP084-P-1818E

QFP084-P-1818E (ES (Engineering Sample) available)

100 ns

Minimum Instruction

Execution Time

100 ns (at 3.135 V to 3.465 V, normal-mode)

 Interrupts

External (5 lines)

Internal (15 lines) : Timer × 4, A/D × 1, RESET × 1, OSD × 1, Serial × 2, Teletext decoder × 2, I²C × 1, Caption × 1, Remote control × 1,

HSYNC× 1, VSYNC× 1

 Timer Counter

8-bit timer × 4

Watchdog timer : Time-out period is selectable.

 Serial interface

I²C × 1 : for multimaster mode, bus line (output) has 2 systems

Sync serial / UART × 1

 Caption / Teletext Decoder

・Built-in sync separator × 1

 I/O Pins

I/O

Common use

 A/D converter

10-bit × 8-ch. (with S/H)

 PWM

8-bit × 4-ch. , 14-bit × 1-ch.

 Special Ports

Remote control reception

 CRTC

1-layer display (graphics, characters, splits)

 Notes

Remote control input discriminant circuit built-in, build-in NTSC/PAL (BGHIDK, M, N)/SECAM/NTSC443 video signal processing

circuit, built-in 3-line comb ﬁlter (NTSC), built-in adaptive 2-line comb ﬁlter (PAL), built-in teletext decoder

 Development tools

In-circuit Emulator

PX-PAC101E02-4W9J

MAD00040EEM

12 3

中文翻译

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