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MM74HC165N_NL

更新时间： 2023-01-03 07:05:34
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管输出元件
页数 文件大小 规格书
6页 136K
描述
HC/UH SERIES, 1-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDIP16, LEAD FREE, PLASTIC, DIP-16

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MM74HC165N_NL 数据手册

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January 1988  
MM54HC165/MM74HC165  
Parallel-in/Serial-out 8-Bit Shift Register  
General Description  
The MM54HC165/MM74HC165 high speed PARALLEL-IN/  
SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-  
gate CMOS technology. It has the low power consumption  
and high noise immunity of standard CMOS integrated cir-  
cuits, along with the ability to drive 10 LS-TTL loads.  
ing is inhibited as long as the SHIFT/LOAD input is high.  
When taken low, data at the parallel inputs is loaded directly  
into the register independent of the state of the clock.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
This 8-bit serial shift register shifts data from Q to Q when  
H
A
clocked. Parallel inputs to each stage are enabled by a low  
level at the SHIFT/LOAD input. Also included is a gated  
CLOCK input and a complementary output from the eighth  
bit.  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
Typical propagation delay: 20 ns (clock to Q)  
Wide operating supply voltage range: 2–6V  
Low input current: 1 mA maximum  
Low quiescent supply current: 80 mA maximum  
(74HC Series)  
Clocking is accomplished through a 2-input NOR gate per-  
mitting one input to be used as a CLOCK INHIBIT function.  
Holding either of the CLOCK inputs high inhibits clocking,  
and holding either CLOCK input low with the SHIFT/LOAD  
input high enables the other CLOCK input. Data transfer  
occurs on the positive going edge of the clock. Parallel load-  
Y
Y
Y
Y
Fanout of 10 LS-TTL loads  
Connection Diagram  
Function Table  
Inputs  
Internal  
Outputs  
Dual-In-Line Package  
Output  
Shift/ Clock  
Parallel  
A . . . H  
Q
H
Clock Serial  
Load Inhibit  
Q
A
Q
B
L
H
H
H
H
X
L
X
L
X
X
H
L
a . . . h  
a
b
h
X
X
X
X
Q
A0  
Q
Q
Q
Q
B0  
H0  
L
H
u
u
X
AN  
AN  
GN  
GN  
L
L
Q
Q
H
X
Q
A0  
Q
Q
H0  
B0  
e
e
e
Low Level (steady state)  
H
X
High Level (steady state), L  
Irrelevant (any input, including transitions)  
e
Transition from low to high level  
u
Q
e
indicated steady-state input conditions were established.  
,
Q
B0  
,
Q
H0  
The level of  
Q , Q , or Q , respectively, before the  
A B H  
A0  
e
the clock; indicates a one-bit shift.  
Q
, Q  
GN  
The level of Q or Q before the most recent  
G
transition of  
u
AN  
A
TL/F/5316–1  
Top View  
Order Number MM54HC165 or MM74HC165  
C
1995 National Semiconductor Corporation  
TL/F/5316  
RRD-B30M105/Printed in U. S. A.  
123456

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