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MM74HC165SJX_NL

更新时间： 2024-11-01 13:11:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器
页数 文件大小 规格书
8页 81K
描述
Parallel In Serial Out, HC/UH Series, 8-Bit, Right Direction, Complementary Output, CMOS, PDSO16, 5.30 MM, EIAJ TYPE2, SOP-16

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MM74HC165SJX_NL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.3
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.31
其他特性：CLOCK INHIBIT计数方向：RIGHT
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：10.1 mm
逻辑集成电路类型：PARALLEL IN SERIAL OUT最大频率@ Nom-Sup：21000000 Hz
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：189 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：5.3 mm最小 fmax：50 MHz
Base Number Matches：1

MM74HC165SJX_NL 数据手册

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September 1983  
Revised February 1999  
MM74HC165  
Parallel-in/Serial-out 8-Bit Shift Register  
loading is inhibited as long as the SHIFT/LOAD input is  
HIGH. When taken LOW, data at the parallel inputs is  
loaded directly into the register independent of the state of  
the clock.  
General Description  
The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT  
SHIFT REGISTER utilizes advanced silicon-gate CMOS  
technology. It has the low power consumption and high  
noise immunity of standard CMOS integrated circuits,  
along with the ability to drive 10 LS-TTL loads.  
The 74HC logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to VCC and ground.  
This 8-bit serial shift register shifts data from QA to QH  
when clocked. Parallel inputs to each stage are enabled by  
a low level at the SHIFT/LOAD input. Also included is a  
gated CLOCK input and a complementary output from the  
eighth bit.  
Features  
■ Typical propagation delay: 20 ns (clock to Q)  
■ Wide operating supply voltage range: 2–6V  
■ Low input current: 1 µA maximum  
Clocking is accomplished through a 2-input NOR gate per-  
mitting one input to be used as a CLOCK INHIBIT function.  
Holding either of the CLOCK inputs high inhibits clocking,  
and holding either CLOCK input low with the SHIFT/LOAD  
input high enables the other CLOCK input. Data transfer  
occurs on the positive going edge of the clock. Parallel  
■ Low quiescent supply current: 80 µA maximum (74HC  
Series)  
■ Fanout of 10 LS-TTL loads  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC165M  
MM74HC165SJ  
MM74HC165MTC  
MM74HC165  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Internal Output  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Shift/ Clock  
Load Inhibit  
Parallel  
QH  
Clock Serial  
Outputs  
A. . .H QA QB  
L
H
H
H
H
X
L
X
L
↑
X
X
H
L
a. . .h  
a
b
h
X
X
X
X
QA0 QB0 QH0  
L
H
L
QAN QGN  
QAN QGN  
L
↑
H
X
X
QA0 QB0 QH0  
H = HIGH Level (steady state), L = LOW Level (steady state)  
X = Irrelevant (any input, including transitions)  
↑ = Transition from LOW-to-HIGH level  
Q
, Q , Q = The level of Q , Q , or Q , respectively, before the indi-  
B0 H0 A B H  
A0  
cated steady-state input conditions were established.  
, Q = The level of Q or Q before the most recent ↑ transition of the  
Q
AN  
GN  
A
G
clock; indicates a one-bit shift.  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005316.prf  
www.fairchildsemi.com  
12345678

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