Datasheet > MM74HC166

MM74HC166

更新时间： 2024-11-01 05:08:35

品牌	Logo	应用领域
美国国家半导体 - NSC		移位寄存器
页数	文件大小	规格书
6页	146K
描述
8-Bit Parallel In/Serial Out Shift Registers

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MM74HC166 数据手册

August 1989

MM54HC166/MM74HC166

8-Bit Parallel In/Serial Out Shift Registers

General Description

The MM54HC166/MM74HC166 high speed 8-BIT PARAL-

LEL-IN/SERIAL-OUT SHIFT REGISTER utilizes advanced

silicon-gate CMOS technology. It has low power consump-

tion and high noise immunity of standard CMOS integrated

circuits, along with the ability to drive 10 LS-TTL loads.

stopped on command with the other clock input. The

CLOCK INHIBIT input should be changed to the high level

only while the clock input is high. A direct CLEAR input over-

rides all other inputs, including the CLOCK, and sets all flip-

flops to zero.

These Parallel-In or Serial-In, Serial-Out shift registers fea-

ture gated CLOCK inputs and an overriding CLEAR input.

The load mode is established by the SHIFT/LOAD input.

When high, this input enables the SERIAL INPUT and cou-

ples the eight flip-flops for serial shifting with each clock

pulse. When low, the PARALLEL INPUTS are enabled and

synchronous loading occurs on the next clock pulse. During

parallel loading, serial data flow is inhibited. Clocking is ac-

complished on the low-to-high level edge of the CLOCK

pulse through a 2-input NOR gate, permitting one input to

be used as a clock enable or CLOCK INHIBIT function.

Holding either of the clock inputs high inhibits clocking;

holding either low enables the other clock input. This allows

the system clock to be free running, and the register can be

The 54HC/74HC logic family is functionally as well as pin

out compatible with the standard 54LS/74LS logic family.

All inputs are protected from damage due to static dis-

charge by internal diode clamps to V

and Ground.

Features

Typical propagation delay:

Wide operating supply voltage range: 2V–6V

Low input current: 1 mA

Low quiescent supply current: 80 mA maximum

(74HC Series)

Fanout of 10 LS-TTL loads

Connection Diagram

Function Table

Inputs

Internal

Outputs Output

Dual-In-Line Package

Shift/ Clock

Parallel

A...H

Clear

Clock Serial

Load Inhibit

A0 B0

a...h

A0 B0

Low Level (steady state)

High Level (steady state), L

Don’t Care (any input, including transitions)

a . . . h

Transition from low to high level

The level of steady-state input at inputs A through H, respectively

The level of Q , Q , Q , respectively, before the indicated

A B H

, Q , Q

B0 H0

steady-state input conditions were established

The level of Q , Q , respectively, before the most recent

A G

, Q

transition of the clock

TL/F/5770–1

Order Number MM54HC166 or MM74HC166

1995 National Semiconductor Corporation

TL/F/5770

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

中文翻译

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与MM74HC166相关器件

型号	品牌	获取价格	描述	数据表
MM74HC166J/A+	TI	获取价格	IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,CERAMIC
MM74HC166M	FAIRCHILD	获取价格	Shift Register, 8-Bit, CMOS, CDSO16,
MM74HC166M/A+	TI	获取价格	IC,SHIFT REGISTER,HC-CMOS,SOP,16PIN,CERAMIC
MM74HC166MX	TI	获取价格	HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLAS
MM74HC166N	FAIRCHILD	获取价格	Shift Register, 8-Bit, CMOS, PDIP16,
MM74HC166N	TI	获取价格	HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, DIP-
MM74HC166N/A+	TI	获取价格	IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC166N/B+	TI	获取价格	IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC173	NSC	获取价格	TRI - STATE-R QUAD D FLIP-FLOP
MM74HC173J	NSC	获取价格	TRI - STATE-R QUAD D FLIP-FLOP

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