MM74HC173J

更新时间： 2024-11-06 10:53:03

品牌	Logo	应用领域
美国国家半导体 - NSC		触发器
页数	文件大小	规格书
6页	125K
描述
TRI - STATE-R QUAD D FLIP-FLOP

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MM74HC173J 数据手册

January 1988

MM54HC173/MM74HC173

TRI-STATE Quad D Flip-Flop

General Description

The MM54HC173/MM74HC173 is a high speed TRI-STATE

QUAD D TYPE FLIP-FLOP that utilizes advanced silicon-

gate CMOS technology. It possesses the low power con-

sumption and high noise immunity of standard CMOS inte-

grated circuits, and can operate at speeds comparable to

the equivalent low power Schottky device. The outputs are

buffered, allowing this circuit to drive 15 LS-TTL loads. The

large output drive capability and TRI-STATE feature make

this part ideally suited for interfacing with bus lines in a bus

oriented system.

the inputs, forcing the flip flops to remain in the same state.

Clearing is enabled by taking the CLEAR input to a logic ‘‘1’’

level. The data outputs change state on the positive going

edge of the clock.

The 54HC/74HC logic family is functionally as well as pin-

out compatible with the standard 54LS/74LS logic family.

All inputs are protected from damage due to static dis-

charge by internal diode clamps to V

and ground.

Features

The four D TYPE FLIP-FLOPS operate synchronously from

a common clock. The TRI-STATE outputs allow the device

to be used in bus organized systems. The outputs are

placed in the TRI-STATE mode when either of the two out-

put disable pins are in the logic ‘‘1’’ level. The input disable

allows the flip-flops to remain in their present states without

having to disrupt the clock. If either of the 2 input disables

are taken to a logic ‘‘1’’ level, the Q outputs are fed back to

Typical propagation delay: 18 ns

Wide operating supply voltage range: 2–6V

TRI-STATE outputs

Low input current: 1 mA maximum

Low quiescent supply current: 80 mA maximum (74HC)

High output drive current: 6 mA minimum

Connection Diagram

Truth Table

Inputs

Dual-In-Line Package

Output

Data Enable

Data

Clear Clock

When either M or N (or both) is (are) high the out-

put is disabled to the high-impedance state: how-

ever, sequential operation of the flip-flops is not

affected.

high level (steady state)

low level (steady state)

low-to-high level transition

don’t care (any input including transitions)

tions were established

the level of Q before the indicated steady state input condi-

TL/F/5317–1

Top View

Order Number MM54HC173 or MM74HC173

TRI-STATE is a registered trademark of National Semiconductor Corp.

1995 National Semiconductor Corporation

TL/F/5317

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

中文翻译

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与MM74HC173J相关器件

型号	品牌	获取价格	描述	数据表
MM74HC173J/A+	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,DIP,16PIN,CERAMIC
MM74HC173M	NSC	获取价格	IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SO-16,
MM74HC173M	TI	获取价格	IC HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SO-16,
MM74HC173M/A+	NSC	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,SOP,16PIN,PLASTIC
MM74HC173M/A+	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,SOP,16PIN,PLASTIC
MM74HC173MX	TI	获取价格	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SO-16
MM74HC173MX	ROCHESTER	获取价格	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SO-16
MM74HC173N	TI	获取价格	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP16, PLASTIC, DIP-16
MM74HC173N/A+	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,DIP,16PIN,PLASTIC
MM74HC173N/B+	TI	获取价格	IC,FLIP-FLOP,QUAD,D TYPE,HC-CMOS,DIP,16PIN,PLASTIC

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