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MM74HC174MX_NL PDF预览

MM74HC174MX_NL

更新时间: 2024-11-21 13:02:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
7页 75K
描述
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16

MM74HC174MX_NL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.65
Is Samacsys:N系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:21000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:6功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):206 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:50 MHzBase Number Matches:1

MM74HC174MX_NL 数据手册

 浏览型号MM74HC174MX_NL的Datasheet PDF文件第2页浏览型号MM74HC174MX_NL的Datasheet PDF文件第3页浏览型号MM74HC174MX_NL的Datasheet PDF文件第4页浏览型号MM74HC174MX_NL的Datasheet PDF文件第5页浏览型号MM74HC174MX_NL的Datasheet PDF文件第6页浏览型号MM74HC174MX_NL的Datasheet PDF文件第7页 
September 1983  
Revised February 1999  
MM74HC174  
Hex D-Type Flip-Flops with Clear  
Each output can drive 10 low power Schottky TTL equiva-  
lent loads. The MM74HC174 is functionally as well as pin  
compatible to the 74LS174. All inputs are protected from  
damage due to static discharge by diodes to VCC and  
General Description  
The MM74HC174 edge triggered flip-flops utilize advanced  
silicon-gate CMOS technology to implement D-type flip-  
flops. They possess high noise immunity, low power, and  
speeds comparable to low power Schottky TTL circuits.  
This device contains 6 master-slave flip-flops with a com-  
mon clock and common clear. Data on the D input having  
the specified setup and hold times is transferred to the Q  
output on the LOW-to-HIGH transition of the CLOCK input.  
The CLEAR input when LOW, sets all outputs to a low  
state.  
ground.  
Features  
Typical propagation delay: 16 ns  
Wide operating voltage range: 2–6V  
Low input current: 1 µA maximum  
Low quiescent current: 80 µA (74HC Series)  
Output drive: 10 LSTTL loads  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC174M  
MM74HC174SJ  
MM74HC174MTC  
MM74HC174N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
(Each Flip-Flop)  
Inputs  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Outputs  
Clear  
Clock  
D
X
H
L
Q
L
L
H
H
H
X
H
L
L
X
Q0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Don't Care  
↑ = Transition from LOW-to-HIGH level  
Q
= The level of Q before the indicated steady state input conditions were  
0
established.  
© 1999 Fairchild Semiconductor Corporation  
DS005318.prf  
www.fairchildsemi.com  

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