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MM74HC175MX PDF预览

MM74HC175MX

更新时间: 2024-11-03 11:10:11
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 239K
描述
带清零功能的四通道 D 型触发器

MM74HC175MX 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:SOP, SOP16,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:0.68系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:24000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
传播延迟(tpd):190 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:70 MHzBase Number Matches:1

MM74HC175MX 数据手册

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DATA SHEET  
www.onsemi.com  
Quad D-Type Flip-Flop With  
Clear  
1
1
MM74HC175  
SOIC16  
CASE 751B  
TSSOP16  
CASE 948F  
Description  
The MM74HC175 high speed Dtype flipflop with  
complementary outputs utilizes advanced silicongate CMOS  
technology to achieve the high noise immunity and low power  
consumption of standard CMOS integrated circuits, along with the  
ability to drive 10 LSTTL loads. Information at the D inputs of the  
MM74HC175 is transferred to the Q and Q outputs on the positive  
going edge of the clock pulse. Both true and complement outputs from  
each flip flop are externally available. All four flipflops are  
controlled by a common clock and a common CLEAR. Clearing is  
accomplished by a negative pulse at the CLEAR input. All four Q  
outputs are cleared to a logical “0” and all four Q outputs to a logical  
“1.” The 74HC logic family is functionally as well as pinout  
compatible with the standard 74LS logic family. All inputs are  
protected from damage due to static discharge by internal diode  
MARKING DIAGRAMS  
16  
1
16  
HC  
HC175A  
AWLYWW  
175A  
ALYW  
1
HC175A = Specific Device Code  
A
L/WL  
Y/YY  
= Assembly Location  
= Wafer Lot  
= Year of Production, Last Number  
W/WW = Work Week Number  
CONNECTION DIAGRAM  
clamps to V and ground.  
CC  
Features  
Typical Propagation Delay: 15 ns  
Wide Operating Supply Voltage Range: 2–6 V  
Low Input Current: 1 mA Maximum  
Low Quiescent Supply Current: 160 mA Maximum (74HC)  
High Output Drive Current: 4 mA Minimum (74HC)  
These are PbFree Devices  
(Top View)  
TRUTH TABLE  
(Each Flip Flop)  
Outputs  
Inputs  
Clock  
D
X
H
Q
Q
H
L
Clear  
L
L
H
H
X
H
L
H
L
Q
Q
H
0
L
0
X
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Irrelevant  
= Transition from LOWtoHIGH level  
Q = The level of Q before the indicated  
0
steadystate input conditions were established  
ORDERING INFORMATION  
See detailed ordering, marking and shipping information in the  
package dimensions section on page 4 of this data sheet.  
Figure 1. Logic Diagram  
© Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
November, 2022 Rev. 1  
MM74HC175/D  

MM74HC175MX 替代型号

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