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MM74HC175MX_NL

更新时间： 2024-11-21 21:03:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
7页 75K
描述
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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MM74HC175MX_NL 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.66系列：HC/UH
JESD-30 代码：R-PDSO-G16JESD-609代码：e3/e4
长度：9.9 mm逻辑集成电路类型：D FLIP-FLOP
位数：4功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：190 ns认证状态：Not Qualified
座面最大高度：1.75 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：70 MHz
Base Number Matches：1

MM74HC175MX_NL 数据手册

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September 1983  
Revised February 1999  
MM74HC175  
Quad D-Type Flip-Flop With Clear  
The 74HC logic family is functionally as well as pin-out  
compatible with the standard 74LS logic family. All inputs  
are protected from damage due to static discharge by inter-  
nal diode clamps to VCC and ground.  
General Description  
The MM74HC175 high speed D-type flip-flop with comple-  
mentary outputs utilizes advanced silicon-gate CMOS  
technology to achieve the high noise immunity and low  
power consumption of standard CMOS integrated circuits,  
along with the ability to drive 10 LS-TTL loads.  
Features  
■ Typical propagation delay: 15 ns  
Information at the D inputs of the MM74HC175 is trans-  
ferred to the Q and Q outputs on the positive going edge of  
the clock pulse. Both true and complement outputs from  
each flip flop are externally available. All four flip-flops are  
controlled by a common clock and a common CLEAR.  
■ Wide operating supply voltage range: 2–6V  
■ Low input current: 1 µA maximum  
■ Low quiescent supply current: 80 µA maximum (74HC)  
■ High output drive current: 4 mA minimum (74HC)  
Clearing is accomplished by  
a negative pulse at the  
CLEAR input. All four Q outputs are cleared to a logical “0”  
and all four Q outputs to a logical “1.”  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC175M  
MM74HC175SJ  
MM74HC175MTC  
MM74HC175N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
(Each Flip-Flop)  
Inputs  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Outputs  
Clear  
Clock  
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
H
H
L
↑
L
H
L
X
Q0  
Q0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Irrelevant  
↑ = Transition from LOW-to-HIGH level  
= The level of Q before the indicated steady-state input conditions were  
Q
0
established  
Top View  
© 1999 Fairchild Semiconductor Corporation  
DS005319.prf  
www.fairchildsemi.com  
1234567

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