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MM74HC174N_NL

更新时间: 2024-11-02 13:11:39
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飞兆/仙童 - FAIRCHILD 触发器
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MM74HC174N_NL 数据手册

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September 1983  
Revised February 1999  
MM74HC174  
Hex D-Type Flip-Flops with Clear  
Each output can drive 10 low power Schottky TTL equiva-  
lent loads. The MM74HC174 is functionally as well as pin  
compatible to the 74LS174. All inputs are protected from  
damage due to static discharge by diodes to VCC and  
General Description  
The MM74HC174 edge triggered flip-flops utilize advanced  
silicon-gate CMOS technology to implement D-type flip-  
flops. They possess high noise immunity, low power, and  
speeds comparable to low power Schottky TTL circuits.  
This device contains 6 master-slave flip-flops with a com-  
mon clock and common clear. Data on the D input having  
the specified setup and hold times is transferred to the Q  
output on the LOW-to-HIGH transition of the CLOCK input.  
The CLEAR input when LOW, sets all outputs to a low  
state.  
ground.  
Features  
Typical propagation delay: 16 ns  
Wide operating voltage range: 2–6V  
Low input current: 1 µA maximum  
Low quiescent current: 80 µA (74HC Series)  
Output drive: 10 LSTTL loads  
Ordering Code:  
Order Number Package Number  
Package Description  
MM74HC174M  
MM74HC174SJ  
MM74HC174MTC  
MM74HC174N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
(Each Flip-Flop)  
Inputs  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Outputs  
Clear  
Clock  
D
X
H
L
Q
L
L
H
H
H
X
H
L
L
X
Q0  
H = HIGH Level (steady state)  
L = LOW Level (steady state)  
X = Don't Care  
↑ = Transition from LOW-to-HIGH level  
Q
= The level of Q before the indicated steady state input conditions were  
0
established.  
© 1999 Fairchild Semiconductor Corporation  
DS005318.prf  
www.fairchildsemi.com  

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