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MM74HC173

更新时间： 2024-02-28 04:28:25
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
6页 125K
描述
TRI - STATE-R QUAD D FLIP-FLOP

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MM74HC173 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.24
其他特性：WITH HOLD MODE; WITH DUAL OUTPUT ENABLE系列：HC/UH
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：19.305 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：21000000 Hz
最大I（ol）：0.006 A位数：4
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V传播延迟（tpd）：44 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.62 mm
最小 fmax：21 MHzBase Number Matches：1

MM74HC173 数据手册

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January 1988  
MM54HC173/MM74HC173  
TRI-STATE Quad D Flip-Flop  
É
General Description  
The MM54HC173/MM74HC173 is a high speed TRI-STATE  
QUAD D TYPE FLIP-FLOP that utilizes advanced silicon-  
gate CMOS technology. It possesses the low power con-  
sumption and high noise immunity of standard CMOS inte-  
grated circuits, and can operate at speeds comparable to  
the equivalent low power Schottky device. The outputs are  
buffered, allowing this circuit to drive 15 LS-TTL loads. The  
large output drive capability and TRI-STATE feature make  
this part ideally suited for interfacing with bus lines in a bus  
oriented system.  
the inputs, forcing the flip flops to remain in the same state.  
Clearing is enabled by taking the CLEAR input to a logic ‘‘1’’  
level. The data outputs change state on the positive going  
edge of the clock.  
The 54HC/74HC logic family is functionally as well as pin-  
out compatible with the standard 54LS/74LS logic family.  
All inputs are protected from damage due to static dis-  
charge by internal diode clamps to V  
and ground.  
CC  
Features  
Y
The four D TYPE FLIP-FLOPS operate synchronously from  
a common clock. The TRI-STATE outputs allow the device  
to be used in bus organized systems. The outputs are  
placed in the TRI-STATE mode when either of the two out-  
put disable pins are in the logic ‘‘1’’ level. The input disable  
allows the flip-flops to remain in their present states without  
having to disrupt the clock. If either of the 2 input disables  
are taken to a logic ‘‘1’’ level, the Q outputs are fed back to  
Typical propagation delay: 18 ns  
Y
Wide operating supply voltage range: 2–6V  
TRI-STATE outputs  
Y
Y
Y
Y
Low input current: 1 mA maximum  
Low quiescent supply current: 80 mA maximum (74HC)  
High output drive current: 6 mA minimum  
Connection Diagram  
Truth Table  
Inputs  
Dual-In-Line Package  
Output  
Q
Data Enable  
Data  
D
Clear Clock  
G1  
G2  
H
L
L
L
L
L
X
X
X
H
X
L
X
X
X
H
L
X
X
X
X
L
L
L
Q
0
Q
0
Q
0
u
u
u
u
L
L
L
H
H
When either M or N (or both) is (are) high the out-  
put is disabled to the high-impedance state: how-  
ever, sequential operation of the flip-flops is not  
affected.  
e
e
e
e
H
L
high level (steady state)  
low level (steady state)  
low-to-high level transition  
u
X
don’t care (any input including transitions)  
e
tions were established  
Q
the level of Q before the indicated steady state input condi-  
O
TL/F/5317–1  
Top View  
Order Number MM54HC173 or MM74HC173  
TRI-STATE is a registered trademark of National Semiconductor Corp.  
É
C
1995 National Semiconductor Corporation  
TL/F/5317  
RRD-B30M105/Printed in U. S. A.  
123456

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