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MM74C923J PDF预览

MM74C923J

更新时间: 2024-09-15 13:11:39
品牌 Logo 应用领域
美国国家半导体 - NSC 编码器
页数 文件大小 规格书
10页 220K
描述
IC CMOS SERIES, 9-BIT ENCODER, CDIP20, CERAMIC, DIP-20, Arithmetic Circuit

MM74C923J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.73
其他特性:20 KEY ENCODER系列:CMOS
JESD-30 代码:R-GDIP-T20JESD-609代码:e0
长度:24.51 mm负载电容(CL):50 pF
逻辑集成电路类型:ENCODER位数:9
功能数量:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5/15 V
传播延迟(tpd):150 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Arithmetic Circuits
最大供电电压 (Vsup):15 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MM74C923J 数据手册

 浏览型号MM74C923J的Datasheet PDF文件第2页浏览型号MM74C923J的Datasheet PDF文件第3页浏览型号MM74C923J的Datasheet PDF文件第4页浏览型号MM74C923J的Datasheet PDF文件第5页浏览型号MM74C923J的Datasheet PDF文件第6页浏览型号MM74C923J的Datasheet PDF文件第7页 
July 1993  
MM54C922/MM74C922 16-Key Encoder  
MM54C923/MM74C923 20-Key Encoder  
General Description  
These CMOS key encoders provide all the necessary logic  
to fully encode an array of SPST switches. The keyboard  
scan can be implemented by either an external clock or  
external capacitor. These encoders also have on-chip pull-  
up devices which permit switches with up to 50 kX on resist-  
ance to be used. No diodes in the switch array are needed  
to eliminate ghost switches. The internal debounce circuit  
needs only a single external capacitor and can be defeated  
by omitting the capacitor. A Data Available output goes to a  
high level when a valid keyboard entry has been made. The  
Data Available output returns to a low level when the en-  
tered key is released, even if another key is depressed. The  
Data Available will return high to indicate acceptance of the  
new key after a normal debounce period; this two-key roll-  
over is provided between any two switches.  
An internal register remembers the last key pressed even  
after the key is released. The TRI-STATE outputs provide  
for easy expansion and bus operation and are LPTTL com-  
patible.  
É
Features  
Y
50 kX maximum switch on resistance  
Y
On or off chip clock  
Y
On-chip row pull-up devices  
Y
2 key roll-over  
Y
Keybounce elimination with single capacitor  
Y
Last key register at outputs  
Y
TRI-STATE outpust LPTTL compatible  
Y
Wide supply range  
3V to 15V  
Y
Low power consumption  
Connection Diagrams  
Pin Assignment for  
Dual-In-Line Package  
Pin Assignment  
for SOIC  
Pin Assignment for  
DIP and SOIC Package  
TL/F/603714  
Top View  
TL/F/6037–1  
Order Number MM74C922  
Top View  
TL/F/6037–2  
Top View  
Order Number MM54C922 or  
MM74C922  
Order Number MM54C923 or  
MM74C923  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6037  
RRD-B30M105/Printed in U. S. A.  

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