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MM54C195F

更新时间: 2024-09-29 13:11:43
品牌 Logo 应用领域
美国国家半导体 - NSC /
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6页 130K
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MM54C195F 数据手册

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February 1988  
MM54C195/MM74C195 4-Bit Registers  
General Description  
Features  
Y
Medium speed operation  
8.5 MHz (typ.) with 10V  
supply and 50 pF load  
The MM54C195/MM74C195 CMOS 4-bit registers feature  
parallel inputs, parallel outputs, J-K serial inputs, shift/load  
control input and a direct overriding clear. The following two  
modes of operation are possible:  
Y
High noise immunity  
0.45 V (typ.)  
CC  
Y
Low power  
100 nW (typ.)  
Drive 2 LPTTL loads  
3V to 15V  
Y
Parallel Load  
Tenth power TTL compatible  
Y
Supply voltage range  
Shift in direction Q towards Q  
A
D
Y
Synchronous parallel load  
Parallel loading is accomplished by applying the four bits of  
data and taking the shift/load control of input low. The data  
is loaded into the associated flip-flops and appears at the  
outputs after the positive transition of the clock input. During  
parallel loading, serial data flow is inhibited.  
Y
Parallel inputs and outputs from each flip-flop  
Direct overriding clear  
Y
Y
Y
Y
Y
J and K inputs to first stage  
Complementary outputs from last stage  
Positive-edge triggered clocking  
Serial shifting is accomplished synchronously when the  
shift/load control input is high. Serial data for this mode is  
entered at the J-K inputs. These inputs allow the first stage  
to perform as a J-K, D, or T-type flip flop as shown in the  
truth table.  
Diode clamped inputs to protect against static charge  
Applications  
Y
Y
Y
Y
Y
Automotive  
Alarm systems  
Remote metering  
Industrial electronics  
Computers  
Y
Data terminals  
Y
Instrumentation  
Y
Medical electronics  
Schematic and Connection Diagrams  
P
Pin 16 to V  
TL/F/5902–1  
CC  
Dual-In-Line Package  
TL/F/5902–2  
Top View  
Order Number MM54C195 or MM74C195  
C
1995 National Semiconductor Corporation  
TL/F/5902  
RRD-B30M105/Printed in U. S. A.  

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