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MCM69R738AZP5R PDF预览

MCM69R738AZP5R

更新时间: 2024-11-10 22:06:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 内存集成电路静态存储器信息通信管理
页数 文件大小 规格书
20页 217K
描述
4M Late Write 2.5 V I/O

MCM69R738AZP5R 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA,
针数:119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.86Is Samacsys:N
最长访问时间:2.5 nsJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:4718592 bit内存集成电路类型:LATE-WRITE SRAM
内存宽度:36功能数量:1
端口数量:1端子数量:119
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX36
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.4 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MCM69R738AZP5R 数据手册

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Order this document  
by MCM69R738A/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69R738A  
MCM69R820A  
Advance Information  
4M Late Write 2.5 V I/O  
TheMCM69R738A/820Aisa4megabitsynchronouslatewritefaststaticRAM  
designed to provide high performance in secondary cache and ATM switch,  
Telecom, and other high speed memory applications. The MCM69R820A  
organized as 256K words by 18 bits, and the MCM69R738A organized as 128K  
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate  
BiCMOS technology.  
The differential CK clock inputs control the timing of read/write operations of  
the RAM. At the rising edge of the CK clock all addresses, write enables, and  
synchronous selects are registered. An internal buffer and special logic enable  
the memory to accept write data on the rising edge of the CK clock a cycle after  
address and control signals. Read data is driven on the rising edge of the CK  
clock also.  
ZP PACKAGE  
PBGA  
CASE 999–01  
The RAM uses 2.5 V inputs and outputs.  
The synchronous write and byte enables allow writing to individual bytes or the  
entire word.  
Byte Write Control  
Single 3.3 V +10%, – 5% Operation  
2.5 V I/O (V  
)
DDQ  
Register to Register Synchronous Operation  
Asynchronous Output Enable  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x 18 or x 36 organization  
MCM69R738A/820A–5 = 5 ns  
MCM69R738A/820A–6 = 6 ns  
MCM69R738A/820A–7 = 7 ns  
MCM69R738A/820A–8 = 8 ns  
Sleep Mode Operation (ZZ Pin)  
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array  
(PBGA) Package  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
8/13/97  
Motorola, Inc. 1997  

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