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MCM69R818CZP4

更新时间: 2024-11-11 11:05:55
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
20页 520K
描述
4M Late Write HSTL

MCM69R818CZP4 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
MOTOROLA  
Order this document  
by MCM69R736C/D  
MCM69R736C  
MCM69R818C  
4M Late Write HSTL  
The MCM69R736C/818C is a 4M–bit synchronous late write fast static RAM  
designed to provide high performance in secondary cache and ATM switch,  
Telecom, and other high speed memory applications. The MCM69R818C  
(organizedas256Kwordsby18bits)andtheMCM69R736C(organizedas128K  
words by 36 bits) are fabricated in Motorola’s high performance silicon gate  
BiCMOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous  
selects are registered. An internal buffer and special logic enable the memory to  
accept write data on the rising edge of CK, a cycle after address and control sig-  
nals. Read data is also driven on the rising edge of CK.  
ZP PACKAGE  
PBGA  
CASE 999–02  
The RAM uses HSTL inputs and outputs. The adjustable input trip–point  
(V ) and output voltage (V  
) gives the system designer greater flexibility in  
ref  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or  
the entire word.  
The impedance of the output buffers is programmable, allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
Byte Write Control  
Single 3.3 V +10%, –5% Operation  
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)  
HSTL — User Selectable Input Trip–Point  
HSTL — Compatible Programmable Impedance Output Drivers  
Register to Register Synchronous Operation  
Asynchronous Output Enable  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 Organization  
MCM69R736C/818C–4 = 4 ns  
MCM69R736C/818C–4.4 = 4.4 ns  
MCM69R736C/818C–5 = 5 ns  
MCM69R736C/818C–6 = 6 ns  
Sleep Mode Operation (ZZ pin)  
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array  
(PBGA) Package  
REV 1  
8/10/99  
Motorola, Inc. 1999  
For More Information On This Product,  
Go to: www.freescale.com  

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