Datasheet > MCM69R738C

MCM69R738C

更新时间： 2024-11-11 11:05:55

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
20页	511K
描述
4M Late Write 2.5 V I/O

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MCM69R738C 数据手册

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

MOTOROLA

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MCM69R738C

MCM69R820C

4M Late Write 2.5 V I/O

The MCM69R738C/820C is a 4M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache and ATM switch,

Telecom, and other high speed memory applications. The MCM69R820C

(organizedas256Kwordsby18bits)andtheMCM69R738C(organizedas128K

words by 36 bits) are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control

signals. Read data is also driven on the rising edge of CK.

ZP PACKAGE

PBGA

CASE 999–02

The RAM uses 2.5 V inputs and outputs.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

•

Byte Write Control

Single 3.3 V +10%, –5% Operation

2.5 V I/O (V

)

DDQ

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM69R738C/820C–4 = 4 ns

MCM69R738C/820C–4.4 = 4.4 ns

MCM69R738C/820C–5 = 5 ns

MCM69R738C/820C–6 = 6 ns

•

Sleep Mode Operation (ZZ Pin)

119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

REV 1

8/13/99

Motorola, Inc. 1999

MOTOROLA FAST SRAM

MCM69R738C•MCM69R820C

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...20

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