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MCM69F819TQ8R PDF预览

MCM69F819TQ8R

更新时间: 2024-09-20 20:22:27
品牌 Logo 应用领域
恩智浦 - NXP 静态存储器内存集成电路
页数 文件大小 规格书
20页 416K
描述
IC,SYNC SRAM,256KX18,CMOS,QFP,100PIN,PLASTIC

MCM69F819TQ8R 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.31.00.01风险等级:5.52
Is Samacsys:N最长访问时间:8 ns
其他特性:FLOW-THROUGH ARCHITECTUREJESD-30 代码:R-PQFP-G100
长度:20 mm内存密度:4718592 bit
内存集成电路类型:CACHE SRAM内存宽度:18
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX18
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MCM69F819TQ8R 数据手册

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Freescale Semiconductor, Inc.  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM69F819/D  
MCM69F819  
256K x 18 Bit Flow–Through  
BurstRAM Synchronous  
Fast Static RAM  
The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide  
a burstable, high performance, secondary cache for the PowerPC and other  
high performance microprocessors. It is organized as 256K words of 18 bits  
each. This device integrates input registers, a 2–bit address counter, and high  
speed SRAM onto a single monolithic circuit for reduced parts count in cache  
dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe  
use of an external clock (K).  
ZP PACKAGE  
PBGA  
CASE 999–02  
Addresses (SA), data inputs (DQx), and all control signals except output  
enable(G) and linear burst order (LBO) are clock (K) controlled through positive
edge–triggered noninverting registers.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst  
addresses can be generated internally by the MCM69F819 (burst sequence  
operates in linear or interleaved mode dependent upon the state of LBO) and  
controlled by the burst address advance (ADV) input pin.  
Write cycles are internally self–timed and are initiated by the rising edge of the  
clock (K) input. This feature eliminates complex of–chip write pulse generation  
and provides increased timing flexibility for incoming signals.  
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-  
nous write enable (SW) are provided to allow writes to either individual bytes or  
to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and  
SBb controls DQb. Individual bytes are written if the selected byte writes SBx are  
asserted with SW. All bytes are written if either SGW is asserted or if all SBx and  
SW are asserted.  
For read cycles, a flow–through SRAM allows output data to simply flow freely  
from the memory array.  
The MCM69F819 operates from a 3.3 V core power supply and all outputs  
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-  
dard JESD8–5 compatible.  
MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)  
MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)  
MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)  
MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)  
3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply  
ADSP, ADSC, and ADV Burst Control Pins  
Selectable Burst Sequencing Order (Linear/Interleaved)  
Single–Cycle Deselect Timing  
Internally Self–Timed Write Cycle  
Byte Write and Global Write Control  
PB1 Version 2.0 Compatible  
JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages  
The PowerPC name is a trademark of IBM Corp., used under license therefrom.  
REV 7  
1/22/98  
Motorola, Inc. 1998  
For More Information On This Product,  
Go to: www.freescale.com  

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