Datasheet > 存储 > SRAM> MCM69F819ZP7.5

MCM69F819ZP7.5

更新时间： 2024-11-07 22:06:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器
页数	文件大小	规格书
20页	278K
描述
256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

MCM69F819ZP7.5 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	119	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.52	Is Samacsys：	N
最长访问时间：	7.5 ns	其他特性：	SELF TIMED WRITE CYCLE; BYTE WRITE CONTROL
备用内存宽度：	18	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	4718592 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	9	功能数量：	1
端口数量：	1	端子数量：	119
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	512KX9
输出特性：	3-STATE	可输出：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	2.4 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

MCM69F819ZP7.5 数据手册

Order this document

by MCM69F819/D

SEMICONDUCTOR TECHNICAL DATA

MCM69F819

256K x 18 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the PowerPC and other

high performance microprocessors. It is organized as 256K words of 18 bits

each. This device integrates input registers, a 2–bit address counter, and high

speed SRAM onto a single monolithic circuit for reduced parts count in cache

dataRAMapplications. Synchronousdesignallowsprecisecyclecontrolwiththe

use of an external clock (K).

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

TQ PACKAGE

TQFP

CASE 983A–01

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F819 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and

SBb controls DQb. Individual bytes are written if the selected byte writes SBx are

asserted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F819 operates from a 3.3 V core power supply and all outputs

operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

•

MCM69F819–7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz)

MCM69F819–8: 8 ns Access/10 ns Cycle (100 MHz)

MCM69F819–8.5: 8.5 ns Access/11 ns Cycle 90 MHz)

MCM69F819–11: 11 ns Access/20 ns Cycle (50 MHz)

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 7

1/22/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69F819

12 3 4 5 6 7...20

中文翻译

下载PDF

与MCM69F819ZP7.5相关器件

型号	品牌	获取价格	描述	数据表
MCM69F819ZP7.5R	MOTOROLA	获取价格	256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F819ZP7.5R	NXP	获取价格	IC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC
MCM69F819ZP8	MOTOROLA	获取价格	256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F819ZP8	NXP	获取价格	IC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC
MCM69F819ZP8.5	MOTOROLA	获取价格	256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F819ZP8.5	NXP	获取价格	IC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC
MCM69F819ZP8.5R	MOTOROLA	获取价格	256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F819ZP8R	MOTOROLA	获取价格	256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
MCM69F819ZP8R	NXP	获取价格	IC,SYNC SRAM,256KX18,CMOS,BGA,119PIN,PLASTIC
MCM69H618FN10	MOTOROLA	获取价格	Cache SRAM, 64KX18, 10ns, BICMOS, PQCC52, PLASTIC, LCC-52

与MCM69F819ZP7.5相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

20
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

18
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

43
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69F819ZP7.5

MCM69F819ZP7.5 技术参数

MCM69F819ZP7.5 数据手册

与MCM69F819ZP7.5相关器件

与MCM69F819ZP7.5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69F819ZP7.5

MCM69F819ZP7.5 技术参数

MCM69F819ZP7.5 数据手册

与MCM69F819ZP7.5相关器件

与MCM69F819ZP7.5相关文章

您还可以找

您在本页遇到什么问题？