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MCM63D736TQ-133 PDF预览

MCM63D736TQ-133

更新时间： 2024-01-14 20:15:57
品牌 Logo 应用领域
恩智浦 - NXP 静态存储器内存集成电路
页数 文件大小 规格书
14页 256K
描述
128KX36 DUAL-PORT SRAM, 4ns, PQFP176, TQFP-176

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中文翻译

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MCM63D736TQ-133 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-176针数：176
Reach Compliance Code：unknown风险等级：5.39
最长访问时间：4 ns备用内存宽度：1
JESD-30 代码：S-PQFP-G176长度：24 mm
内存密度：4718592 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：36功能数量：1
端子数量：176字数：131072 words
字数代码：128000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX36封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE, FINE PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：24 mm
Base Number Matches：1

MCM63D736TQ-133 数据手册

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Order this document  
by MCM63D736/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM63D736  
128K x 36 Bit Synchronous  
Dual I/O, Dual Address SRAM  
The MCM63D736 is a 4M–bit static random access memory, organized as  
128K words of 36 bits. It features common data input and data output buffers and  
incorporates input and output registers on–board with high speed SRAM.  
The MCM63D736 allows the user to concurrently perform reads, writes, or  
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
TQ PACKAGE  
176 LEAD TQFP  
CASE 1101–01  
The pass–through feature allows data to be passed from one port to the other,  
in either direction. The PTX input must be asserted to pass data from port X to  
port Y. The PTY will likewise pass data from port Y to port X. A pass–through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain protocols are followed. If  
both ports are read, the reads occur normally. If one port is written and the other  
is read, the read from the array will occur before the data is written. If both ports  
are written, only the data on DQY will be written to the array.  
•
•
•
•
•
Single 3.3 V ±5% Power Supply  
Fast Access Times: 4/5 ns Max  
Throughput of 4.8 Gigabits/Second  
Single Clock Operation  
Address, Data Input, E1X, E2X, E1Y, E2Y, PTX, PTY, WX, WY, and Data  
Output Registers On–Chip  
•
•
•
•
•
•
•
•
•
133 MHz Maximum Clock Frequency  
Self–Timed Write  
Two Bi–Directional Data Buses  
Can be Configured as Separate I/O  
Pass–Through Feature  
Asynchronous Output Enables (GX, GY)  
LVTTL Compatible I/O  
Concurrent Reads and Writes  
176–Pin TQFP Package  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cellular Base Stations  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory — RAID Systems  
Product Family Configurations  
Frequency  
(MHz)  
Supply  
Voltage  
I/O  
Voltage  
Single  
Clock  
Dual  
Clock  
Yes  
Yes  
No  
Density  
16M  
8M  
Package  
209 PBGA  
Availability  
100  
100  
2.5/1.8 V  
3.3/2.5 V  
3.3 V  
2.5/1.8 V  
3.3/2.5 V  
3.3 V  
Yes  
Yes  
Yes  
Yes  
Samples 4Q00  
Samples 2Q00  
In Production  
In Production  
209 PBGA  
4M  
100/133  
83/100  
176 TQFP  
1M  
3.3 V  
3.3 V  
No  
100, 176 TQFP  
REV 2  
11/29/99  
Motorola, Inc. 1999  
1234567...14

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