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MCM63D736TQ83 PDF预览

MCM63D736TQ83

更新时间: 2024-02-09 17:01:05
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 内存集成电路静态存储器
页数 文件大小 规格书
16页 450K
描述
128K x 36 Bit Synchronous Dual I/O, Dual Address SRAM

MCM63D736TQ83 技术参数

生命周期:Obsolete包装说明:LFQFP,
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:6 nsJESD-30 代码:S-PQFP-G176
长度:24 mm内存密度:4718592 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
功能数量:1端子数量:176
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX36
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:24 mmBase Number Matches:1

MCM63D736TQ83 数据手册

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Order this document  
by MCM63D736/D  
Freescale Semiconductor  
MCM63D736  
128K x 36 Bit Synchronous  
Dual I/O, Dual Address SRAM  
The MCM63D736 is a 4M–bit static random access memory, organized as  
128K words of 36 bits. It features common data input and data output buffers and  
incorporates input and output registers on–board with high speed SRAM.  
The MCM63D736 allows the user to concurrently perform reads, writes, or  
pass–throughcyclesincombinationonthetwodataports. Thetwoaddressports  
(AX, AY) determine the read or write locations for their respective data ports  
(DQX, DQY).  
The synchronous design allows for precise cycle control with the use of an  
external single clock (K). All signal pins except output enables (GX, GY) are  
registered on the rising edge of clock (K).  
TQ PACKAGE  
176 LEAD TQFP  
CASE 1101–01  
The pass–through feature allows data to be passed from one port to the other,  
in either direction. The PTX input must be asserted to pass data from port X to  
port Y. The PTY will likewise pass data from port Y to port X. A pass–through  
operation takes precedence over a read operation.  
For the case when AX and AY are the same, certain protocols are followed. If  
both ports are read, the reads occur normally. If one port is written and the other  
is read, the read from the array will occur before the data is written. If both ports  
are written, only the data on DQY will be written to the array.  
Single 3.3 V ±5% Power Supply  
133 MHz Maximum Clock Frequency  
Throughput of 4.8 Gigabits/Second  
Single Clock Operation  
Self–Timed Write  
Two Bi–Directional Data Buses  
Can be Configured as Separate I/O  
Pass–Through Feature  
Asynchronous Output Enables (GX, GY)  
LVTTL Compatible I/O  
Concurrent Reads and Writes  
176–Pin TQFP Package  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cellular Base Stations  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory — RAID Systems  
© Freescale Semiconductor, Inc., 2004. All rights reserved.  
REV 4  
7/6/00  
For More Information On This Product,  
Go to: www.freescale.com  

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