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MC74VHC1GT14DFT2 PDF预览

MC74VHC1GT14DFT2

更新时间: 2024-11-04 05:30:07
品牌 Logo 应用领域
ETL 转换器电平转换器触发器
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4页 577K
描述
Schmitt-Trigger Inverter/ CMOS Logic Level Shifter with LSTTL-Compatible Inputs

MC74VHC1GT14DFT2 数据手册

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Schmitt-Trigger Inverter/ CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
MC74VHC1GT14  
The MC74VHC1GT14 is a single gate CMOS Schmitt–trigger inverter fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and the output has a full 5 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from  
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power  
supply.  
The MC74VHC1GT14 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT14 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when  
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,  
battery backup, hot insertion, etc. The MC74VHC1GT14 can be used to enhance noise immunity or to square up slowly changing waveforms.  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• High Speed: t PD = 4.5 ns (Typ) at V CC = 5 V  
• Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C  
• TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V  
• Pin and Function Compatible with Other Standard Logic  
Families  
• CMOS–Compatible Outputs: V OH > 0.8 V CC  
V OL < 0.1 V CC @ Load  
;
• Chip Complexity: FETs = 100; Equivalent Gates = 25  
MARKING DIAGRAMS  
5
4
1
2
3
VCd  
SC–70/SC–88A/SOT–353  
DF SUFFIX  
CASE 419A  
Pin 1  
d = Date Code  
5
Figure 1. Pinout (Top View)  
4
VCd  
1
2
3
Figure 2. Logic Symbol  
SOT–23/TSOP–5/SC–59  
DT SUFFIX  
CASE 483  
Pin 1  
d = Date Code  
PIN ASSIGNMENT  
FUNCTION TABLE  
1
2
3
4
5
NC  
IN A  
Inputs  
Output  
A
L
Y
H
L
GND  
OUT Y  
V CC  
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the  
package dimensions section on page 4 of this data sheet.  
VHT14–1/4  

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