Datasheet > MC74VHC1GT126_07

MC74VHC1GT126_07

更新时间： 2024-11-04 05:30:07

品牌	Logo	应用领域
安森美 - ONSEMI		转换器电平转换器
页数	文件大小	规格书
6页	87K
描述
Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

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MC74VHC1GT126_07 数据手册

MC74VHC1GT126

Noninverting Buffer /

CMOS Logic Level Shifter

with LSTTL−Compatible Inputs

The MC74VHC1GT126 is a single gate noninverting 3−state buffer

fabricated with silicon gate CMOS technology. It achieves high speed

operation similar to equivalent Bipolar Schottky TTL while maintaining

CMOS low power dissipation.

The MC74VHC1GT126 requires the 3−state control input (OE) to be

set Low to place the output into the high impedance state.

http://onsemi.com

MARKING

DIAGRAMS

The device input is compatible with TTL−type input thresholds and

the output has a full 5 V CMOS level output swing. The input

protection circuitry on this device allows overvoltage tolerance on the

input, allowing the device to be used as a logic−level translator from

3 V CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to

3 V CMOS Logic while operating at the high−voltage power supply.

The MC74VHC1GT126 input structure provides protection when

voltages up to 7 V are applied, regardless of the supply voltage. This

allows the MC74VHC1GT126 to be used to interface 5 V circuits to

3 V circuits. The output structures also provide protection when

W3 M G

SC−88A/SOT−353/SC−70

DF SUFFIX

CASE 419A

W3 M G

TSOP−5/SOT−23/SC−59

DT SUFFIX

= 0 V. These input and output structures help prevent device

destruction caused by supply voltage − input/output voltage mismatch,

battery backup, hot insertion, etc.

CASE 483

Features

W3 = Device Code

• High Speed: t = 3.5 ns (Typ) at V = 5 V

• Low Power Dissipation: I = 1 mA (Max) at T = 25°C

• TTL−Compatible Inputs: V = 0.8 V; V = 2 V

• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load

= Date Code*

= Pb−Free Package

(Note: Microdot may be in either location)

*Date Code orientation and/or position may vary

depending upon manufacturing location.

• Power Down Protection Provided on Inputs and Outputs

• Balanced Propagation Delays

• Pin and Function Compatible with Other Standard Logic Families

• Chip Complexity: FETs = 62; Equivalent Gates = 16

• Pb−Free Packages are Available

PIN ASSIGNMENT

IN A

GND

OUT Y

IN A

GND

FUNCTION TABLE

OE Input

OUT Y

A Input

Y Output

Figure 1. Pinout (Top View)

IN A

OUT Y

ORDERING INFORMATION

Figure 2. Logic Symbol

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Semiconductor Components Industries, LLC, 2007

Publication Order Number:

February, 2007 − Rev. 13

MC74VHC1GT126/D

12 3 4 5 6

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与MC74VHC1GT126_07相关器件

型号	品牌	获取价格	描述	数据表
MC74VHC1GT126_09	ONSEMI	获取价格	Noninverting Buffer / CMOS Logic Level Shifter with LSTTL.Compatible Inputs
MC74VHC1GT126_18	ONSEMI	获取价格	Noninverting 3-State Buffer
MC74VHC1GT126DBVT1G	ONSEMI	获取价格	Noninverting 3-State Buffer
MC74VHC1GT126DF1	ONSEMI	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
MC74VHC1GT126DF1G	ONSEMI	获取价格	AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
MC74VHC1GT126DF2	ONSEMI	获取价格	Noninverting Buffer / CMOS Logic Level Shifter
MC74VHC1GT126DF2G	ONSEMI	获取价格	AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
MC74VHC1GT126DFT	MOTOROLA	获取价格	AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
MC74VHC1GT126DT	ONSEMI	获取价格	暂无描述
MC74VHC1GT126DT1	ONSEMI	获取价格	Noninverting Buffer / CMOS Logic Level Shifter

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