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MC74VHC1GT126DTT

更新时间： 2024-11-04 14:43:27
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 260K
描述
Bus Driver, AHC/VHC Series, 1-Func, 1-Bit, True Output, CMOS, PDSO5, SC-59, SOT-23, TSOP-5

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MC74VHC1GT126DTT 技术参数

生命周期：Obsolete包装说明：TSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65系列：AHC/VHC
JESD-30 代码：R-PDSO-G5长度：3 mm
逻辑集成电路类型：BUS DRIVER位数：1
功能数量：1端口数量：2
端子数量：5最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE传播延迟（tpd）：16 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL宽度：1.5 mm
Base Number Matches：1

MC74VHC1GT126DTT 数据手册

 浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第2页浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第3页浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第4页浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第5页浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第6页浏览型号MC74VHC1GT126DTT的Datasheet PDF文件第7页 
with LSTTL–Compatible Inputs  
http://onsemi.com  
The MC74VHC1GT126 is a single gate noninverting 3–state buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
MARKING DIAGRAM  
The MC74VHC1GT126 requires the 3–state control input (OE) to  
be set Low to place the output into the high impedance state.  
The device input is compatible with TTL–type input thresholds and  
the output has a full 5V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic–level translator from  
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to  
3.0V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT126 input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT126 to be used to interface 5V circuits to  
SC–88A / SOT–353/SC–70  
DF SUFFIX  
d
W3  
CASE 419A  
Pin 1  
d = Date Code  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
d
W3  
CASE 483A  
3V circuits. The output structures also provide protection when V  
=
CC  
Pin 1  
0V. These input and output structures help prevent device destruction  
caused by supply voltage – input/output voltage mismatch, battery  
backup, hot insertion, etc.  
d = Date Code  
• High Speed: t  
= 3.5ns (Typ) at V  
= 5V  
PD  
• Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
PIN ASSIGNMENT  
CC  
A
1
2
3
4
5
OE  
IN A  
GND  
• TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
• CMOS–CompatibleOutputs: V  
• Power Down Protection Provided on Inputs and Outputs  
• Balanced Propagation Delays  
• Pin and Function Compatible with Other Standard Logic Families  
• Latchup Performance Exceeds 300mA  
IL  
IH  
> 0.8V ; V < 0.1V @Load  
OH  
CC OL CC  
OUT Y  
VCC  
• ESD Performance: HBM > 1500V; MM > 200V  
ORDERING INFORMATION  
Seedetailedorderingandshippinginformationinthepackage  
dimensions section on page 4 of this data sheet.  
OE  
IN A  
GND  
VCC  
1
2
3
5
4
OUT Y  
FUNCTION TABLE  
Figure 1. 5–Lead SOT–353 Pinout (Top View)  
A Input  
OE Input  
Y Output  
LOGIC SYMBOL  
L
H
X
H
H
L
L
H
Z
OE  
OUT Y  
IN A  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
June, 2000 – Rev. 1  
MC74VHC1GT126/D  
1234567...12

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