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MC74VHC1GT14 PDF预览

MC74VHC1GT14

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器触发器
页数 文件大小 规格书
8页 189K
描述
Schmitt-Trigger Inverter/CMOS Logic Level Shifter

MC74VHC1GT14 数据手册

 浏览型号MC74VHC1GT14的Datasheet PDF文件第2页浏览型号MC74VHC1GT14的Datasheet PDF文件第3页浏览型号MC74VHC1GT14的Datasheet PDF文件第4页浏览型号MC74VHC1GT14的Datasheet PDF文件第5页浏览型号MC74VHC1GT14的Datasheet PDF文件第6页浏览型号MC74VHC1GT14的Datasheet PDF文件第7页 
with LSTTL–Compatible Inputs  
The MC74VHC1GT14 is a single gate CMOS Schmitt–trigger  
inverter fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and  
the output has a full 5V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic–level translator from  
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to  
3.0V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT14 input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT14 to be used to interface 5V circuits to 3V  
SC–88A / SOT–353  
DF SUFFIX  
CASE 419A  
MARKING DIAGRAM  
circuits. The output structures also provide protection when V  
= 0V.  
CC  
d
VC  
These input and output structures help prevent device destruction  
caused by supply voltage – input/output voltage mismatch, battery  
backup, hot insertion, etc. The MC74VHC1GT14 can be used to  
enhance noise immunity or to square up slowly changing waveforms.  
Pin 1  
d = Date Code  
High Speed: t  
= 4.5ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
1
2
3
4
5
NC  
IN A  
GND  
IL  
IH  
CMOS–CompatibleOutputs: V  
> 0.8V ; V < 0.1V @Load  
OH  
CC OL CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
OUT Y  
VCC  
NC  
IN A  
GND  
VCC  
1
2
3
5
4
ORDERING INFORMATION  
Seedetailedorderingandshippinginformationinthepackage  
dimensions section on page 4 of this data sheet.  
OUT Y  
Figure 1. 5–Lead SOT–353 Pinout (Top View)  
FUNCTION TABLE  
LOGIC SYMBOL  
A Input  
Y Output  
IN A  
L
H
L
OUT Y  
H
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
November, 1999 – Rev. 1  
MC74VHC1GT14/D  

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