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MC74VHC1GT126DF2 PDF预览

MC74VHC1GT126DF2

更新时间: 2024-11-03 22:20:23
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
页数 文件大小 规格书
8页 107K
描述
Noninverting Buffer / CMOS Logic Level Shifter

MC74VHC1GT126DF2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:SC-70, SC-88A, SOT-353, 5 PIN
针数:5Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.42
控制类型:ENABLE HIGH系列:AHC/VHC
JESD-30 代码:R-PDSO-G5JESD-609代码:e0
长度:2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP5/6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:3.3/5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1.25 mm
Base Number Matches:1

MC74VHC1GT126DF2 数据手册

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MC74VHC1GT126  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL−Compatible Inputs  
The MC74VHC1GT126 is a single gate noninverting 3−state buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The MC74VHC1GT126 requires the 3−state control input (OE) to be  
set Low to place the output into the high impedance state.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The device input is compatible with TTL−type input thresholds and the  
output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logic−level translator from 3.0 V  
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V  
CMOS Logic while operating at the high−voltage power supply.  
The MC74VHC1GT126 input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT126 to be used to interface 5 V circuits to 3 V  
SC−88A / SOT−353/SC−70  
DF SUFFIX  
W3d  
CASE 419A  
Pin 1  
d = Date Code  
TSOP−5/SOT−23/SC−59  
DT SUFFIX  
W3d  
circuits. The output structures also provide protection when V = 0 V.  
CC  
CASE 483  
These input and output structures help prevent device destruction caused  
by supply voltage − input/output voltage mismatch, battery backup, hot  
insertion, etc.  
Pin 1  
d = Date Code  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
1
2
3
4
5
OE  
IN A  
CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 62; Equivalent Gates = 16  
OH  
CC  
OL  
CC  
GND  
OUT Y  
V
CC  
FUNCTION TABLE  
OE Input  
A Input  
Y Output  
OE  
IN A  
GND  
5
4
V
CC  
1
2
3
L
H
X
H
H
L
L
H
Z
OUT Y  
Figure 1. Pinout (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
OE  
IN A  
OUT Y  
Figure 2. Logic Symbol  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
December, 2003 − Rev. 9  
MC74VHC1GT126/D  

MC74VHC1GT126DF2 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHC1GT126DF1G ONSEMI

完全替代

AHC/VHC SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN
MC74VHC1GT126DF1 ONSEMI

完全替代

Noninverting Buffer / CMOS Logic Level Shifter
M74VHC1GT126DF1G ONSEMI

功能相似

Noninverting Buffer / CMOS Logic Level Shifter with LSTTL−Compatible Inputs

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