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MC74VHC1GT125DTT3 PDF预览

MC74VHC1GT125DTT3

更新时间: 2024-02-19 12:36:08
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 137K
描述
IC,BUFFER/DRIVER,SINGLE,1-BIT,AHC/VHC-CMOS,TSOP,5PIN,PLASTIC

MC74VHC1GT125DTT3 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:TSOP, TSOP5/6,.11,37Reach Compliance Code:unknown
风险等级:5.87控制类型:ENABLE LOW
JESD-30 代码:R-PDSO-G5JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A位数:1
功能数量:1端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE包装方法:TAPE AND REEL
电源:3.3/5 VProp。Delay @ Nom-Sup:10.5 ns
认证状态:Not Qualified子类别:Bus Driver/Transceivers
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUALBase Number Matches:1

MC74VHC1GT125DTT3 数据手册

 浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第2页浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第3页浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第4页浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第5页浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第6页浏览型号MC74VHC1GT125DTT3的Datasheet PDF文件第7页 
MC74VHC1GT125  
Product Preview  
Noninverting Buffer /  
CMOS Logic Level Shifter  
with LSTTL–Compatible Inputs  
http://onsemi.com  
The MC74VHC1GT125 is a single gate noninverting buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
MARKING  
DIAGRAMS  
The MC74VHC1GT125 requires the 3–state control input (OE) to  
be set High to place the output into the high impedance state.  
The device input is compatible with TTL–type input thresholds and  
the output has a full 5V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic–level translator from  
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to  
3.0V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT125 input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This allows  
the MC74VHC1GT125 to be used to interface 5V circuits to 3V circuits.  
SC–88A / SOT–353/SC–70  
DF SUFFIX  
d
W1  
CASE 419A  
Pin 1  
d = Date Code  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
d
W1  
CASE 483  
The output structures also provide protection when V = 0V. These input  
and output structures help prevent device destruction caused by supply  
voltage – input/output voltage mismatch, battery backup, hot insertion, etc.  
CC  
Pin 1  
d = Date Code  
High Speed: t = 3.5ns (Typ) at V = 5V  
PD  
CC  
Low Power Dissipation: I = 2µA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
IL  
IH  
1
2
3
4
5
OE  
IN A  
GND  
CMOS–Compatible Outputs: V > 0.8V ; V < 0.1V @Load  
OH  
CC OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
OUT Y  
VCC  
ESD Performance: HBM > 1500V; MM > 200V  
ORDERING INFORMATION  
OE  
IN A  
GND  
1
2
3
5
4
VCC  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
OUT Y  
Figure 1. 5–Lead SOT–353 Pinout (Top View)  
FUNCTION TABLE  
A Input  
OE Input  
Y Output  
L
H
X
L
L
L
H
Z
OE  
OUT Y  
IN A  
H
Figure 2. Logic Symbol  
This document contains information on a product under development. ON Semiconductor  
reserves the right to change or discontinue this product without notice.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
August, 2000 – Rev. 3  
MC74VHC1GT125/D  

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