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MC74HC4046BDTR2G

更新时间： 2024-09-16 02:51:19
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
13页 181K
描述
Phase-Locked Loop

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MC74HC4046BDTR2G 数据手册

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MC74HC4046B  
Phase-Locked Loop  
High−Performance Silicon−Gate CMOS  
The MC74HC4046B is similar in function to the MC14046 Metal  
gate CMOS device. The device inputs are compatible with standard  
CMOS outputs; with pullup resistors, they are compatible with  
LSTTL outputs.  
www.onsemi.com  
The HC4046B phase−locked loop contains three phase  
comparators, a voltage−controlled oscillator (VCO) and unity gain  
op−amp DEM  
. The comparators have two common signal inputs,  
OUT  
COMP , and SIG . Input SIG and COMP can be used directly  
IN  
IN  
IN  
IN  
SOIC−16  
D SUFFIX  
CASE 751B  
TSSOP−16  
DT SUFFIX  
CASE 948F  
coupled to large voltage signals, or indirectly coupled (with a series  
capacitor to small voltage signals). The self−bias circuit adjusts small  
voltage signals in the linear region of the amplifier. Phase comparator  
1 (an exclusive OR gate) provides a digital error signal PC1  
and  
OUT  
PIN ASSIGNMENT  
maintains 90 degrees phase shift at the center frequency between  
SIG and COMP signals (both at 50% duty cycle). Phase  
IN  
IN  
PCP  
PC1  
1
2
16  
V
CC  
out  
comparator 2 (with leading−edge sensing logic) provides digital error  
signals PC2 and PCP and maintains a 0 degree phase shift  
15 PC3  
14 SIG  
out  
out  
OUT  
OUT  
COMP  
VCO  
3
4
between SIG and COMP signals (duty cycle is immaterial). The  
in  
in  
IN  
IN  
linear VCO produces an output signal VCO  
whose frequency is  
13 PC2  
12 R2  
11 R1  
OUT  
out  
INH  
C1A  
out  
determined by the voltage of input VCO signal and the capacitor  
IN  
5
6
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain  
op−amp output DEM  
with an external resistor is used where the  
OUT  
C1B  
7
8
10 DEM  
VCO signal is needed but no loading can be tolerated. The inhibit  
out  
IN  
input, when high, disables the VCO and all op−amps to minimize  
standby power consumption.  
GND  
9
VCO  
in  
Applications include FM and FSK modulation and demodulation,  
frequency synthesis and multiplication, frequency discrimination,  
tone decoding, data synchronization and conditioning, voltage−to−  
frequency conversion and motor speed control.  
MARKING DIAGRAMS  
16  
HC4046BG  
AWLYWW  
Features  
• Output Drive Capability: 10 LSTTL Loads  
1
SOIC−16  
• Low Power Consumption Characteristic of CMOS Devices  
• Operating Speeds Similar to LSTTL  
16  
HC40  
46B  
• Wide Operating Voltage Range for VCO: 3.0 to 6.0 V  
• Low Input Current: 1.0 ꢀ A Maximum (except SIG and COMP )  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7 A  
ALYWG  
IN  
IN  
G
1
TSSOP−16  
• Low Quiescent Current: 80 ꢀ A Maximum (VCO disabled)  
• High Noise Immunity Characteristic of CMOS Devices  
• Diode Protection on All Inputs  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
W, WW = Work Week  
G or G  
= Pb−Free Package  
• Chip Complexity: 279 FETs or 70 Equivalent Gates  
(Note: Microdot may be in either location)  
• NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 11 of  
this data sheet.  
© Semiconductor Components Industries, LLC, 2018  
1
Publication Order Number:  
May, 2018 − Rev. 1  
MC74HC4046B/D  
1234567...13

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