SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the
MC54/74HC4050 consists of six noninverting buffers. They are identical in
pinout to the MC14049UB and MC14050B metal–gate CMOS buffers. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
The input protection circuitry on these devices has been modified by
eliminating the V
diodes to allow the use of input voltages up to 15 volts.
CC
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
Thus, the devices may be used as logic–level translators that convert from a
high voltage to a low voltage while operating at the low–voltage power
supply. They allow MC14000–series CMOS operating up to 15 volts to be
interfaced with High–Speed CMOS at 2 to 6 volts. The protection diodes to
GND are Zener diodes, which protect the inputs from both positive and
negative voltage transients.
16
1
D SUFFIX
16
SOIC PACKAGE
CASE 751B–05
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
1
Low Input Current: 5 µA
ORDERING INFORMATION
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXD
Ceramic
Plastic
SOIC
•
Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)
24 FETs or 6 Equivalent Gates (4050)
PIN ASSIGNMENT
LOGIC DIAGRAMS
V
1
2
16
15
NC
Y5
A5
NC
Y4
A4
Y3
A3
CC
Y0
HC4049
HC4050
(INVERTING BUFFER)
(NONINVERTING BUFFER)
A0
Y1
A1
Y2
A2
3
4
5
6
7
8
14
13
12
11
10
9
2
3
5
7
2
4
6
A0
A1
A2
Y0
Y1
Y2
A0
A1
A2
Y0
Y1
Y2
4
GND
7
6
10
12
15
NC = NO CONNECTION
9
9
10
12
15
A3
A4
A5
Y3
Y4
A3
A4
A5
Y3
Y4
Y5
FUNCTION TABLE
Y Outputs
11
14
11
14
A
Input
HC4049 HC4060
L
H
H
L
L
H
Y5
PIN 1 = V
CC
PIN 8 = GND
PINS 13, 16 = NO CONNECTION
10/95
REV 6
1
Motorola, Inc. 1995