MC74HC4050ND

更新时间： 2024-11-06 12:59:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
6页	181K
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MC74HC4050ND 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

The MC54/74HC4049 consists of six inverting buffers, and the

MC54/74HC4050 consists of six noninverting buffers. They are identical in

pinout to the MC14049UB and MC14050B metal–gate CMOS buffers. The

device inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

The input protection circuitry on these devices has been modified by

eliminating the V

diodes to allow the use of input voltages up to 15 volts.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

Thus, the devices may be used as logic–level translators that convert from a

high voltage to a low voltage while operating at the low–voltage power

supply. They allow MC14000–series CMOS operating up to 15 volts to be

interfaced with High–Speed CMOS at 2 to 6 volts. The protection diodes to

GND are Zener diodes, which protect the inputs from both positive and

negative voltage transients.

D SUFFIX

SOIC PACKAGE

CASE 751B–05

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

Low Input Current: 5 µA

ORDERING INFORMATION

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

MC54HCXXXXJ

MC74HCXXXXN

MC74HCXXXXD

Ceramic

Plastic

SOIC

•

Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)

24 FETs or 6 Equivalent Gates (4050)

PIN ASSIGNMENT

LOGIC DIAGRAMS

HC4049

HC4050

(INVERTING BUFFER)

(NONINVERTING BUFFER)

GND

NC = NO CONNECTION

FUNCTION TABLE

Y Outputs

Input

HC4049 HC4060

PIN 1 = V

PIN 8 = GND

PINS 13, 16 = NO CONNECTION

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5 6

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