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MC74HC138NS

更新时间: 2024-11-24 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器解复用器
页数 文件大小 规格书
7页 114K
描述
Decoder/Driver, CMOS, PDIP16

MC74HC138NS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:NJESD-30 代码:R-PDIP-T16
JESD-609代码:e0逻辑集成电路类型:OTHER DECODER/DRIVER
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:2/6 V
认证状态:Not Qualified子类别:Decoder/Drivers
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

MC74HC138NS 数据手册

 浏览型号MC74HC138NS的Datasheet PDF文件第2页浏览型号MC74HC138NS的Datasheet PDF文件第3页浏览型号MC74HC138NS的Datasheet PDF文件第4页浏览型号MC74HC138NS的Datasheet PDF文件第5页浏览型号MC74HC138NS的Datasheet PDF文件第6页浏览型号MC74HC138NS的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC54/74HC138A is identical in pinout to the LS138. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
The HC138A decodes a three–bit Address to one–of–eight active–low  
outputs. This device features three Chip Select inputs, two active–low and  
one active–high to facilitate the demultiplexing, cascading, and chip–select-  
ing functions. The demultiplexing function is accomplished by using the  
Address inputs to select the desired device output; one of the Chip Selects is  
used as a data input while the other Chip Selects are held in their active  
states.  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
16  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
1
Chip Complexity: 100 FETs or 29 Equivalent Gates  
LOGIC DIAGRAM  
ORDERING INFORMATION  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
Ceramic  
Plastic  
SOIC  
1
2
3
15  
A0  
A1  
A2  
Y0  
14  
13  
12  
ADDRESS  
INPUTS  
Y1  
Y2  
Y3  
TSSOP  
ACTIVE–LOW  
OUTPUTS  
11  
10  
Y4  
Y5  
Y6  
Y7  
PIN ASSIGNMENT  
9
7
A0  
A1  
1
2
16  
15  
14  
13  
V
CC  
Y0  
Y1  
Y2  
6
4
3
4
5
6
A2  
CS1  
CS2  
CHIP–  
SELECT  
INPUTS  
PIN 16 = V  
PIN 8 = GND  
CC  
CS2  
5
CS3  
CS1  
12  
11  
Y3  
Y4  
CS3  
7
8
10  
9
Y7  
Y5  
Y6  
FUNCTION TABLE  
GND  
Inputs  
Outputs  
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H = high level (steady state); L = low level (steady state);  
X = don’t care  
10/95  
Motorola, Inc. 1995  
REV 6  

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