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MC74HC139AD PDF预览

MC74HC139AD

更新时间: 2024-11-01 23:05:43
品牌 Logo 应用领域
安森美 - ONSEMI 解码器解复用器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
8页 142K
描述
Dual 1-of-4 Decoder/Demultiplexer

MC74HC139AD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.75系列:HC/UH
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):240
电源:2/6 VProp。Delay @ Nom-Sup:35 ns
传播延迟(tpd):175 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

MC74HC139AD 数据手册

 浏览型号MC74HC139AD的Datasheet PDF文件第2页浏览型号MC74HC139AD的Datasheet PDF文件第3页浏览型号MC74HC139AD的Datasheet PDF文件第4页浏览型号MC74HC139AD的Datasheet PDF文件第5页浏览型号MC74HC139AD的Datasheet PDF文件第6页浏览型号MC74HC139AD的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC139A is identical in pinout to the LS139. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
This device consists of two independent 1–of–4 decoders, each of  
which decodes a two–bit Address to one–of–four active–low outputs.  
Active–low Selects are provided to facilitate the demultiplexing and  
cascading functions. The demultiplexing function is accomplished by  
using the Address inputs to select the desired device output, and  
utilizing the Select as a data input.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC139AN  
AWLYYWW  
16  
16  
1
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
16  
SO–16  
D SUFFIX  
CASE 751B  
HC139A  
AWLYWW  
1
Low Input Current: 1.0 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
A
= Assembly Location  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
SELECT  
a
1
2
16  
15  
V
2
3
4
5
6
7
CC  
SELECT  
Y0  
A0  
ADDRESS  
INPUTS  
a
a
A0  
a
b
Y1  
a
A1  
a
ACTIVE–LOW  
OUTPUTS  
3
4
14  
13  
A1  
a
A0  
b
Y2  
a
Y0  
a
A1  
b
Y3  
a
Y1  
a
5
6
7
8
12 Y0  
b
PIN 16 = V  
CC  
PIN 8 = GND  
Y2  
a
11  
10  
9
Y1  
1
b
SELECT  
a
Y2  
Y3  
a
b
14  
13  
12  
11  
10  
9
GND  
Y3  
b
Y0  
ADDRESS  
INPUTS  
A0  
b
b
A1  
b
Y1  
b
ACTIVE–LOW  
OUTPUTS  
Y2  
b
Y3  
b
ORDERING INFORMATION  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
Shipping  
15  
SELECT  
b
MC74HC139AN  
MC74HC139AD  
MC74HC139ADR2  
2000 / Box  
48 / Rail  
FUNCTION TABLE  
Inputs  
Select A1 A0  
Outputs  
Y0 Y1 Y2 Y3  
2500 / Reel  
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
X = don’t care  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 7  
MC74HC139A/D  

MC74HC139AD 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC139ADR2G ONSEMI

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Dual 1−of−4 Decoder/ Demultiplexer
MC74HC139ADG ONSEMI

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Dual 1−of−4 Decoder/ Demultiplexer
CD74HC139M TI

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High-Speed CMOS Logic Dual 2-to-4 Line Decoder/Demultiplexer

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