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MC74HC139AND PDF预览

MC74HC139AND

更新时间: 2024-02-02 00:50:01
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 185K
描述
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MC74HC139AND 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
The MC54/74HC139A is identical in pinout to the LS139. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
1
This device consists of two independent 1–of–4 decoders, each of which  
decodes a two–bit Address to one–of–four active–low outputs. Active–low  
Selects are provided to facilitate the demultiplexing and cascading functions.  
The demultiplexing function is accomplished by using the Address inputs to  
select the desired device output, and utilizing the Select as a data input.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Low Input Current: 1.0 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXAD  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
2
3
4
5
6
7
Y0  
Y1  
A0  
A1  
SELECT  
1
2
16  
15  
ADDRESS  
INPUTS  
V
a
a
a
CC  
a
A0  
SELECT  
a
ACTIVE–LOW  
OUTPUTS  
a
b
Y2  
Y3  
3
4
14  
13  
a
A1  
Y0  
Y1  
Y2  
A0  
b
a
a
a
a
A1  
b
a
5
6
12  
11  
Y0  
Y1  
Y2  
Y3  
b
b
b
b
1
SELECT  
a
7
8
10  
9
Y3  
a
14  
13  
12  
11  
10  
9
GND  
Y0  
Y1  
Y2  
Y3  
ADDRESS  
INPUTS  
A0  
A1  
b
b
b
b
b
b
ACTIVE–LOW  
OUTPUTS  
FUNCTION TABLE  
Inputs  
Select A1 A0  
Outputs  
Y0 Y1 Y2 Y3  
15  
SELECT  
b
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
PIN 16 = V  
CC  
PIN 8 = GND  
H
H
X = don’t care  
10/95  
REV 6  
Motorola, Inc. 1995  

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