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MC74HC147DS PDF预览

MC74HC147DS

更新时间: 2024-11-02 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 编码器
页数 文件大小 规格书
5页 83K
描述
暂无描述

MC74HC147DS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC147 is identical in pinout to the LS147. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
This device encodes nine active–low data inputs to four active–low BCD  
Address Outputs, ensuring that only the highest order active data line is  
encoded. The implied decimal zero condition is encoded when all nine data  
inputs are at a high level (inactive).  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
ORDERING INFORMATION  
Low Input Current: 1 µA  
MC74HCXXXN  
MC74HCXXXD  
Plastic  
SOIC  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 136 FETs or 34 Equivalent Gates  
PIN ASSIGNMENT  
D4  
D5  
1
2
16  
15  
V
CC  
NC  
LOGIC DIAGRAM  
D6  
D7  
D8  
3
4
5
14  
13  
12  
A3  
D3  
D2  
11  
D1  
12  
D2  
13  
D3  
D4  
D5  
D6  
D7  
D8  
D9  
9
7
6
A2  
6
11  
D1  
A0  
A1  
A2  
A3  
1
2
BCD  
ADDRESS  
OUTPUTS  
(ACTIVE–LOW)  
A1  
7
8
10  
9
D9  
A0  
DECIMAL  
DATA INPUTS  
(ACTIVE–LOW)  
GND  
3
14  
NC = NO CONNECTION  
4
5
10  
FUNCTION TABLE  
Inputs  
V
= PIN 16  
Outputs  
CC  
GND = PIN 8  
NO CONNECTION = PIN 15  
D9 D8 D7 D6 D5 D4 D3 D2 D1 A3 A2 A1 A0  
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
X
X
X
H
H
H
H
H
L
X
X
X
X
H
H
H
H
L
X
X
X
X
X
H
H
H
L
X
X
X
X
X
X
H
H
L
X
X
X
X
X
X
X
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
H
L
H
L
H
L
X
X
X
X
X
X
X
X
L
H
H
L
L
L
L
L
X
X
H
H
H
H
H
L
X
L
10/95  
Motorola, Inc. 1995  
REV 6  

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