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MC74HC14ADTEL PDF预览

MC74HC14ADTEL

更新时间: 2024-11-02 21:16:55
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
8页 138K
描述
IC,LOGIC GATE,HEX INVERTER,HC-CMOS,TSSOP,14PIN,PLASTIC

MC74HC14ADTEL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSSOP, TSSOP14,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.82
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.0024 A端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:55 ns
认证状态:Not Qualified施密特触发器:YES
子类别:Gates表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
Base Number Matches:1

MC74HC14ADTEL 数据手册

 浏览型号MC74HC14ADTEL的Datasheet PDF文件第2页浏览型号MC74HC14ADTEL的Datasheet PDF文件第3页浏览型号MC74HC14ADTEL的Datasheet PDF文件第4页浏览型号MC74HC14ADTEL的Datasheet PDF文件第5页浏览型号MC74HC14ADTEL的Datasheet PDF文件第6页浏览型号MC74HC14ADTEL的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC14A is identical in pinout to the LS14, LS04 and the  
HC04. The device inputs are compatible with Standard CMOS  
outputs; with pullup resistors, they are compatible with LSTTL  
outputs.  
The HC14A is useful to “square up” slow input rise and fall times.  
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds  
applications in noisy environments.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC14AN  
AWLYYWW  
Output Drive Capability: 10 LSTTL Loads  
1
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 60 FETs or 15 Equivalent Gates  
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HC14A  
AWLYWW  
1
14  
HC  
14A  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
LOGIC DIAGRAM  
1
3
5
2
4
6
1
A1  
A2  
A3  
Y1  
Y2  
Y3  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
FUNCTION TABLE  
Y = A  
Inputs  
A
Outputs  
9
8
10  
12  
A4  
A5  
A6  
Y4  
Y5  
Y6  
Pin 14 = V  
Pin 7 = GND  
Y
CC  
L
H
L
11  
13  
H
Pinout: 14–Lead Packages (Top View)  
ORDERING INFORMATION  
V
A6  
13  
Y6  
12  
A5  
11  
Y5  
10  
A4  
9
Y4  
8
CC  
Device  
Package  
PDIP–14  
Shipping  
14  
MC74HC14AN  
2000 / Box  
55 / Rail  
MC74HC14AD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
MC74HC14ADR2  
MC74HC14ADT  
MC74HC14ADTR2  
2500 / Reel  
96 / Rail  
2500 / Reel  
1
2
3
4
5
6
7
A1  
Y1  
A2  
Y2  
A3  
Y3 GND  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC14A/D  

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