High–Performance Silicon–Gate CMOS
The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 1–of–4 decoders, each of
which decodes a two–bit Address to one–of–four active–low outputs.
Active–low Selects are provided to facilitate the demultiplexing and
cascading functions. The demultiplexing function is accomplished by
using the Address inputs to select the desired device output, and
utilizing the Select as a data input.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP–16
N SUFFIX
CASE 648
MC74HC139AN
AWLYYWW
16
16
1
1
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 2.0 to 6.0 V
16
SO–16
D SUFFIX
CASE 751B
HC139A
AWLYWW
1
• Low Input Current: 1.0 µA
1
• High Noise Immunity Characteristic of CMOS Devices
A
= Assembly Location
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
WL = Wafer Lot
YY = Year
WW = Work Week
• Chip Complexity: 100 FETs or 25 Equivalent Gates
LOGIC DIAGRAM
PIN ASSIGNMENT
SELECT
a
1
2
16
15
V
2
3
4
5
6
7
CC
SELECT
Y0
A0
ADDRESS
INPUTS
a
a
A0
a
b
Y1
a
A1
a
ACTIVE–LOW
OUTPUTS
3
4
14
13
A1
a
A0
b
Y2
a
Y0
a
A1
b
Y3
a
Y1
a
5
6
7
8
12 Y0
b
PIN 16 = V
CC
PIN 8 = GND
Y2
a
11
10
9
Y1
1
b
SELECT
a
Y2
Y3
a
b
14
13
12
11
10
9
GND
Y3
b
Y0
ADDRESS
INPUTS
A0
b
b
A1
b
Y1
b
ACTIVE–LOW
OUTPUTS
Y2
b
Y3
b
ORDERING INFORMATION
Device
Package
PDIP–16
SOIC–16
SOIC–16
Shipping
15
SELECT
b
MC74HC139AN
MC74HC139AD
MC74HC139ADR2
2000 / Box
48 / Rail
FUNCTION TABLE
Inputs
Select A1 A0
Outputs
Y0 Y1 Y2 Y3
2500 / Reel
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
X = don’t care
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 7
MC74HC139A/D