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MC74HC109NS

更新时间: 2024-11-18 13:11:19
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摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
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MC74HC109NS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
High–Performance Silicon–Gate CMOS  
16  
The MC74HC109 is identical in pinout to the LS109. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
This device consists of two J–K flip–flops with individual set, reset, and  
clock inputs. Changes at the inputs are reflected at the outputs with the next  
low–to–high transition of the clock. Both Q and Q outputs are available from  
each flip–flop.  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
MC74HCXXXN  
MC74HCXXXD  
Plastic  
SOIC  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
PIN ASSIGNMENT  
Chip Complexity: 148 FETs or 37 Equivalent Gates  
RESET 1  
J1  
1
2
16  
15  
V
CC  
RESET 2  
K1  
3
4
14  
13  
J2  
LOGIC DIAGRAM  
CLOCK 1  
K2  
SET 1  
5
6
12  
11  
CLOCK 2  
SET 2  
5
SET 1  
Q1  
Q1  
3
4
6
7
K1  
Q1  
Q1  
7
8
10  
9
Q2  
Q2  
CLOCK 1  
GND  
2
1
J1  
FUNCTION TABLE  
Inputs  
RESET 1  
Outputs  
Set Reset Clock  
J
K
Q
Q
11  
SET 2  
L
H
L
H
L
L
X
X
X
X
X
X
L
H
L
X
X
X
L
H
L
H*  
L
L
H
H*  
H
13  
12  
10  
9
K2  
Q2  
Q2  
H
H
H
H
H
H
H
H
H
H
CLOCK 2  
L
Toggle  
No Change  
H
14  
15  
H
H
X
J2  
H
X
L
L
No Change  
RESET 2  
* Both outputs will remain high as long as Set and  
Reset are low, but the output states are unpre-  
dictable if Set and Reset go high simultaneously.  
PIN 16 = V  
CC  
PIN 8 = GND  
10/95  
REV 6  
Motorola, Inc. 1995  

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