MC54HC354JS

更新时间： 2024-11-14 13:02:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		复用器锁存器
页数	文件大小	规格书
9页	210K
描述
Multiplexer, 1-Func, 8 Line Input, CMOS, CDIP20

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中文翻译

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技术参数
数据手册

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MC54HC354JS 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Is Samacsys：	N	JESD-30 代码：	R-XDIP-T20
JESD-609代码：	e0	逻辑集成电路类型：	MULTIPLEXER
功能数量：	1	输入次数：	8
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
封装主体材料：	CERAMIC	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	2/6 V
认证状态：	Not Qualified	子类别：	Multiplexer/Demultiplexers
表面贴装：	NO	技术：	CMOS
温度等级：	MILITARY	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	Base Number Matches：	1

MC54HC354JS 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

High–Performance Silicon–Gate CMOS

The MC54/74HC354 is identical in pinout to the LS354. The device

inputs are compatible with Standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

The HC354 selects one of eight latched binary Data Inputs, as deter-

mined by the Address Inputs. The information at the Data Inputs is stored

in the transparent 8–bit Data Latch when the Data–Latch Enable pin is

held high. The Address information may be stored in the transparent

Address Latch, which is enabled by the active–high Address–Enable pin.

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

The device outputs are placed in high–impedance states when Output

Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXDW

Ceramic

Plastic

SOIC

The HC354 has a clocked Data Latch that is not transparent.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2 to 6V

Pinout: 20–Lead Package (Top View)

• Low Input Current: 1µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 326 FETs or 81.5 Equivalent Gates

LOGIC DIAGRAM

OE3

OE2

OE1

8–BIT

DATA

LATCH

(TRANS–

PARENT)

14 A0

8–BIT

MULTI–

PLEXER

3–STATE

OUTPUT

CONTROL

3–STATE

DATA

OUTPUTS

DATA

INPUTS

Data–Latch

Enable

Address–Latch

Enable

GND

DATA–LATCH

ENABLE

ADDRESS

LATCH

(TRANS–

PARENT)

ADDRESS

INPUTS

PIN 20 = V

PIN 10 = GND

ADDRESS–LATCH

ENABLE

OE1

OUTPUT

ENABLES

OE2

OE3

10/95

Motorola, Inc. 1995

REV 7

12 3 4 5 6 7...9

中文翻译

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与MC54HC354JS相关器件

型号	品牌	获取价格	描述	数据表
MC54HC365	MOTOROLA	获取价格	Hex 3-State Noninverting Buffer with Common Enables
MC54HC365	FREESCALE	获取价格	Hex 3-State Noninverting Buffer with Common Enables
MC54HC365J	MOTOROLA	获取价格	Hex 3-State Noninverting Buffer with Common Enables
MC54HC366	MOTOROLA	获取价格	Hex 3-State Inverting Buffer with Common Enables
MC54HC366	FREESCALE	获取价格	Hex 3-State Inverting Buffer with Common Enables
MC54HC366J	MOTOROLA	获取价格	Hex 3-State Inverting Buffer with Common Enables
MC54HC367	MOTOROLA	获取价格	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC54HC367J	MOTOROLA	获取价格	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC54HC367JD	MOTOROLA	获取价格	暂无描述
MC54HC367JDS	MOTOROLA	获取价格	暂无描述

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