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MC54HC366 PDF预览

MC54HC366

更新时间: 2024-11-14 11:08:55
品牌 Logo 应用领域
飞思卡尔 - FREESCALE /
页数 文件大小 规格书
5页 167K
描述
Hex 3-State Inverting Buffer with Common Enables

MC54HC366 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
16  
16  
The MC54/74HC366 is identical in pinout to the LS366. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device is a high–speed hex buffer with 3–state outputs and two  
common active–low Output Enables. When either of the enables is high, the  
buffer outputs are placed into high–impedance states. The HC366 has  
inverting outputs.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
ORDERING INFORMATION  
Low Input Current: 1 µA  
MC54HCXXXJ  
MC74HCXXXN  
Ceramic  
Plastic  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
Chip Complexity: 78 FETs or 19.5 Equivalent Gates  
PIN ASSIGNMENT  
OUTPUT  
1
2
16  
15  
V
CC  
OUTPUT  
ENABLE 2  
ENABLE 1  
LOGIC DIAGRAM  
A0  
Y0  
A1  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
A5  
Y5  
A4  
Y4  
A3  
Y3  
2
4
3
5
A0  
A1  
Y0  
Y1  
Y1  
A2  
Y2  
6
7
9
A2  
A3  
A4  
Y2  
Y3  
Y4  
GND  
10  
12  
14  
11  
13  
FUNCTION TABLE  
Inputs  
Output  
Y
A5  
Y5  
Enable Enable  
1
2
A
1
OUTPUT ENABLE 1  
OUTPUT ENABLE 2  
PIN 16 = V  
PIN 8 = GND  
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
CC  
15  
X = don’t care  
Z = high impedance  
10/95  
REV 6  
Motorola, Inc. 1995  

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