MC54HC393JDS

更新时间： 2024-11-14 13:11:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		计数器
页数	文件大小	规格书
9页	122K
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MC54HC393JDS 数据手册

SEMICONDUCTOR TECHNICAL DATA

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

High–Performance Silicon–Gate CMOS

The MC54/74HC393A is identical in pinout to the LS393. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of two independent 4–bit binary ripple counters with

parallel outputs from each counter stage. A ÷ 256 counter can be obtained

by cascading the two binary counters.

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

Internal flip–flops are triggered by high–to–low transitions of the clock

input. Reset for the counters is asynchronous and active–high. State

changes of the Q outputs do not occur simultaneously because of internal

ripple delays. Therefore, decoded output signals are subject to decoding

spikes and should not be used as clocks or as strobes except when gated

with the Clock of the HC393A.

D SUFFIX

SOIC PACKAGE

CASE 751A–03

DT SUFFIX

TSSOP PACKAGE

CASE 948G–01

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

ORDERING INFORMATION

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

MC54HCXXXAJ

Ceramic

Plastic

SOIC

MC74HCXXXAN

MC74HCXXXAD

MC74HCXXXADT

TSSOP

•

Chip Complexity: 236 FETs or 59 Equivalent Gates

PIN ASSIGNMENT

LOGIC DIAGRAM

CLOCK a

RESET a

CLOCK b

RESET b

3, 11

4, 10

1, 13

2, 12

BINARY

COUNTER

CLOCK

RESET

5, 9

6, 8

GND

PIN 14 = V

PIN 7 = GND

FUNCTION TABLE

Inputs

Clock

Reset

Outputs

No Change

Advance to

Next State

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/95

REV 0

Motorola, Inc. 1995

12 3 4 5 6 7...9

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