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MC54HC374 PDF预览

MC54HC374

更新时间: 2024-10-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
7页 235K
描述
Octal 3-State Noninverting D Flip-Flop

MC54HC374 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC374A is identical in pinout to the LS374. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
Data meeting the setup time is clocked to the outputs with the rising edge  
of the clock. The Output Enable input does not affect the states of the  
flip–flops, but when Output Enable is high, the outputs are forced to the  
high–impedance state; thus, data may be stored even when the outputs are  
not enabled.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
The HC374A is identical in function to the HC574A which has the input  
pins on the opposite side of the package from the output. This device is  
similar in function to the HC534A which has inverting outputs.  
20  
20  
20  
1
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
1
Low Input Current: 1.0 µA  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
Chip Complexity: 266 FETs or 66.5 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
MC74HCXXXAN  
MC74HCXXXADW  
MC74HCXXXASD  
MC74HCXXXADT  
LOGIC DIAGRAM  
2
3
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
5
6
4
7
PIN ASSIGNMENT  
8
9
DATA  
INPUTS  
OUTPUT  
ENABLE  
NONINVERTING  
OUTPUTS  
1
20  
V
CC  
13  
14  
17  
18  
12  
15  
16  
19  
Q0  
D0  
D1  
2
3
4
19  
18  
17  
Q7  
D7  
D6  
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
11  
CLOCK  
6
Q5  
D2  
7
D5  
D3  
8
D4  
1
PIN 20 = V  
PIN 10 = GND  
CC  
OUTPUT ENABLE  
Q3  
9
Q4  
GND  
10  
CLOCK  
FUNCTION TABLE  
Inputs  
Output  
Output  
Enable Clock  
D
Q
L
L
H
L
H
L
L
H
L,H,  
X
X
X
No Change  
Z
X = don’t care  
Z = high impedance  
10/95  
REV 6  
Motorola, Inc. 1995  

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