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MC54HC390J PDF预览

MC54HC390J

更新时间: 2024-11-14 00:01:07
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
9页 111K
描述
Dual 4-Stage Binary Ripple Counter with ±2 and ±5 Sections

MC54HC390J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.21其他特性:DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS
计数方向:UP系列:HC/UH
JESD-30 代码:R-CDIP-T16长度:19.495 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:DECADE COUNTER最大频率@ Nom-Sup:18000000 Hz
最大I(ol):0.004 A工作模式:ASYNCHRONOUS
位数:3功能数量:4
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V传播延迟(tpd):435 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:21 MHzBase Number Matches:1

MC54HC390J 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
÷
÷
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC390 is identical in pinout to the LS390. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
This device consists of two independent 4–bit counters, each composed  
of a divide–by–two and a divide–by–five section. The divide–by–two and  
divide–by–five counters have separate clock inputs, and can be cascaded to  
implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.  
Flip–flops internal to the counters are triggered by high–to–low transitions  
of the clock input. A separate, asynchronous reset is provided for each 4–bit  
counter. State changes of the Q outputs do not occur simultaneously  
because of internal ripple delays. Therefore, decoded output signals are  
subject to decoding spikes and should not be used as clocks or strobes  
except when gated with the Clock of the HC390.  
16  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
ORDERING INFORMATION  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No 7A  
PIN ASSIGNMENT  
Chip Complexity: 244 FETs or 61 Equivalent Gates  
CLOCK A  
1
2
16  
15  
V
CC  
a
CLOCK A  
RESET a  
b
b
Q
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
RESET b  
Aa  
LOGIC DIAGRAM  
CLOCK B  
Q
Ab  
a
Q
Q
CLOCK B  
Ba  
Q
÷
2
Ca  
Da  
Bb  
3, 13  
5, 11  
1, 15  
Q
Q
A
CLOCK A  
COUNTER  
Q
Q
Cb  
Db  
GND  
Q
B
÷
5
6, 10  
7, 9  
4, 12  
2, 14  
FUNCTION TABLE  
Q
Q
CLOCK B  
RESET  
C
D
COUNTER  
Clock  
A
B
Reset  
Action  
X
X
H
Reset  
÷ 2 and ÷ 5  
X
L
L
Increment  
÷ 2  
PIN 16 = V  
CC  
PIN 8 = GND  
X
Increment  
÷ 5  
10/95  
REV 6  
Motorola, Inc. 1995  

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