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MC54HC373A PDF预览

MC54HC373A

更新时间: 2024-10-15 00:01:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
9页 127K
描述
Octal 3-State Non-Inverting Transparent Latch

MC54HC373A 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
High–Performance Silicon–Gate CMOS  
20  
20  
The MC54/74HC373A is identical in pinout to the LS373. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes low,  
data meeting the setup and hold time becomes latched.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
The Output Enable input does not affect the state of the latches, but when  
Output Enable is high, all device outputs are forced to the high–impedance  
state. Thus, data may be latched even when the outputs are not enabled.  
The HC373A is identical in function to the HC573A which has the data  
inputs on the opposite side of the package from the outputs to facilitate PC  
board layout.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
20  
20  
1
SD SUFFIX  
SSOP PACKAGE  
CASE 940C–03  
1
The HC373A is the non–inverting version of the HC533A.  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
1
ORDERING INFORMATION  
Low Input Current: 1.0 µA  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
SSOP  
TSSOP  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
MC74HCXXXAN  
MC74HCXXXADW  
MC74HCXXXASD  
MC74HCXXXADT  
Chip Complexity: 186 FETs or 46.5 Equivalent Gates  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
OUTPUT  
ENABLE  
Q0  
2
5
1
20  
V
3
CC  
D0  
D1  
D2  
D3  
D4  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
2
3
19  
18  
Q7  
D7  
4
D0  
D1  
6
7
4
17  
D6  
8
9
DATA  
INPUTS  
NONINVERTING  
OUTPUTS  
Q1  
Q2  
5
16  
15  
14  
13  
12  
11  
Q6  
Q5  
D5  
D4  
Q4  
13  
12  
15  
16  
19  
6
14  
17  
18  
D5  
D6  
D7  
D2  
7
D3  
8
Q3  
9
LATCH  
ENABLE  
GND  
10  
11  
1
PIN 20 = V  
CC  
PIN 10 = GND  
LATCH ENABLE  
OUTPUT ENABLE  
FUNCTION TABLE  
Inputs  
Output  
Design Criteria  
Internal Gate Count*  
Value  
46.5  
1.5  
Units  
ea  
Output Latch  
Enable Enable  
D
Q
L
L
L
H
H
L
H
L
X
X
H
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
ns  
L
No Change  
Z
5.0  
µW  
pJ  
H
X
Speed Power Product  
0.0075  
X = Don’t Care  
Z = High Impedance  
* Equivalent to a two–input NAND gate.  
3/97  
REV 7  
Motorola, Inc. 1997  

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