5秒后页面跳转
MC10EP35DR2 PDF预览

MC10EP35DR2

更新时间: 2024-11-24 22:18:03
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 84K
描述
JK Flip Flop

MC10EP35DR2 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列:10EJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:3000000000 Hz
湿度敏感等级:1位数:2
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):50 mA
Prop。Delay @ Nom-Sup:0.575 ns传播延迟(tpd):0.49 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
Base Number Matches:1

MC10EP35DR2 数据手册

 浏览型号MC10EP35DR2的Datasheet PDF文件第2页浏览型号MC10EP35DR2的Datasheet PDF文件第3页浏览型号MC10EP35DR2的Datasheet PDF文件第4页浏览型号MC10EP35DR2的Datasheet PDF文件第5页浏览型号MC10EP35DR2的Datasheet PDF文件第6页浏览型号MC10EP35DR2的Datasheet PDF文件第7页 
The MC10EP35 is a higher speed/low voltage version of the EL35  
JK flip flop. The J/K data enters the master portion of the flip flop  
when the clock is LOW and is transferred to the slave, and thus the  
outputs, upon a positive transition of the clock. The reset pin is  
asynchronous and is activated with a logic HIGH.  
http://onsemi.com  
300ps Propagation Delay  
High Bandwidth to 3 GHz Typical  
High Bandwidth Output Transistors  
8
PECL mode: 3.0V to 5.5V V  
with V = 0V  
CC  
EE  
1
ECL mode: 0V V  
CC  
with V = –3.0V to –5.5V  
EE  
SO–8  
D SUFFIX  
CASE 751  
75k Internal Input Pulldown Resistors  
Q Output will default LOW with inputs open or at V  
ESD Protection: >4KV HBM, >200V MM  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
EE  
MARKING DIAGRAM  
8
1
A = Assembly Location  
L = Wafer Lot  
Y = Year  
HEP35  
ALYW  
W = Work Week  
Transistor Count = 77 devices  
*For additional information, see Application Note  
AND8002/D  
J
1
2
8
7
V
CC  
J
PIN DESCRIPTION  
PIN  
FUNCTION  
CLK  
J, K  
ECL Clock Inputs  
ECL Signal Inputs  
K
Q
Q
K
Flip Flop  
RESET  
Q, Q  
ECL Asynchronous Reset  
ECL Data Outputs  
CLK  
3
4
6
5
R
TRUTH TABLE  
RESET  
V
EE  
J
K
RESET  
CLK  
Qn+1  
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Z
Z
Z
Z
X
Qn  
L
H
Qn  
L
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
Z = LOW to HIGH Transition  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC10EP35D  
SOIC  
98 Units/Rail  
MC10EP35DR2  
SOIC  
2500 Tape & Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
September, 1999 – Rev. 1.0  
MC10EP35/D  

MC10EP35DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP35DR2G ONSEMI

类似代替

3.3V / 5V ECL JK Flip−Flop

与MC10EP35DR2相关器件

型号 品牌 获取价格 描述 数据表
MC10EP35DR2G ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop
MC10EP35DR2G ROCHESTER

获取价格

10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, LEAD FREE,
MC10EP35DT ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop
MC10EP35DT ROCHESTER

获取价格

10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, PLASTIC, T
MC10EP35DTG ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop
MC10EP35DTG ROCHESTER

获取价格

10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, LEAD FREE,
MC10EP35DTR2 ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop
MC10EP35DTR2G ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop
MC10EP35DTR2G ROCHESTER

获取价格

10E SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8, LEAD FREE,
MC10EP35MNR4 ONSEMI

获取价格

3.3V / 5V ECL JK Flip−Flop