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MC10116_02 PDF预览

MC10116_02

更新时间: 2024-11-06 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 108K
描述
Triple Line Receiver

MC10116_02 数据手册

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MC10116  
Triple Line Receiver  
The MC10116 is a triple differential amplifier designed for use in  
sensing differential signals over long lines. The base bias supply  
(V ) is made available at pin 11 to make the device useful as a  
BB  
Schmitt trigger, or in other applications where a stable reference  
voltage is necessary.  
Active current sources provide the MC10116 with excellent  
common mode noise rejection. If any amplifier in a package is not  
http://onsemi.com  
MARKING  
DIAGRAMS  
used, one input of that amplifier must be connected to V (pin 11) to  
prevent upsetting the current source bias network.  
BB  
16  
Complementary outputs are provided to allow driving twisted pair  
lines, to enable cascading of several amplifiers in a chain, or simply to  
provide complement outputs of the input logic function.  
CDIP–16  
L SUFFIX  
CASE 620  
MC10116L  
AWLYYWW  
P = 85 mW typ/pkg (No Load)  
D
1
t = 2.0 ns typ  
pd  
16  
t , t = 2.0 ns typ (20%–80%)  
r
f
PDIP–16  
P SUFFIX  
CASE 648  
MC10116P  
AWLYYWW  
LOGIC DIAGRAM  
4
5
2
3
1
1
9
6
7
PLCC–20  
FN SUFFIX  
CASE 775  
10116  
10  
AWLYYWW  
12  
13  
14  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
15  
11  
CC2  
V
EE  
A
= Assembly Location  
V
BB  
*
WL = Wafer Lot  
YY = Year  
WW = Work Week  
*V to be used to supply bias to the MC10116 only and bypassed (when used)  
BB  
with 0.01 µF to 0.1 µF capacitor to ground (0 V). V can source < 1.0 mA.  
BB  
When the input pin with the bubble goes positive, the output pin with the bubble  
goes positive.  
ORDERING INFORMATION  
DIP  
Device  
Package  
Shipping  
PIN ASSIGNMENT  
MC10116L  
CDIP–16  
25 Units / Rail  
V
A
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
MC10116P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
C
C
C
C
V
OUT  
OUT  
IN  
OUT  
MC10116FN  
A
OUT  
A
IN  
A
IN  
IN  
B
OUT  
B
OUT  
BB  
B
B
IN  
V
IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10116/D  

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