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MC10117PD PDF预览

MC10117PD

更新时间: 2024-11-06 13:00:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA
页数 文件大小 规格书
5页 108K
描述
OR-AND/OR-AND-Invert Gate, ECL10K, PDIP16

MC10117PD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T16
JESD-609代码:e0逻辑集成电路类型:OR-AND/OR-AND-INVERT GATE
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:-5.2 V施密特触发器:NO
子类别:Gates表面贴装:NO
技术:ECL10K温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
Base Number Matches:1

MC10117PD 数据手册

 浏览型号MC10117PD的Datasheet PDF文件第2页浏览型号MC10117PD的Datasheet PDF文件第3页浏览型号MC10117PD的Datasheet PDF文件第4页浏览型号MC10117PD的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10117 is a dual 2–wide 2–3–input OR–AND/OR–AND–Invert gate.  
This general purpose logic element is designed for use in data control, such as  
digital multiplexing or data distribution. Pin 9 is common to both gates.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
t
= 100 mW typ/pkg (No Load)  
= 2.3 ns typ  
D
pd  
t , t = 2.2 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
FN SUFFIX  
PLCC  
CASE 775–02  
LOGIC DIAGRAM  
4
5
DIP  
PIN ASSIGNMENT  
3
2
6
7
V
A
V
B
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
CC2  
OUT  
OUT  
OUT  
OUT  
9
A
10  
11  
B1  
A1  
A1  
A2  
A2  
V
IN  
IN  
IN  
IN  
IN  
IN  
14  
15  
B1  
12  
13  
B2  
B2  
IN  
IN  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
A2 , B2  
IN  
CC1  
CC2  
EE  
IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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