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MC10117L PDF预览

MC10117L

更新时间: 2024-11-05 04:59:43
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
8页 109K
描述
Dual 2-Wide 2-3-Input OR-AND/OR-AND Gate

MC10117L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.48
Is Samacsys:N系列:10K
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.49 mm逻辑集成电路类型:OR-AND/OR-AND-INVERT GATE
功能数量:2输入次数:5
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:-5.2 V最大电源电流(ICC):29 mA
Prop。Delay @ Nom-Sup:3.8 ns传播延迟(tpd):3.4 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
表面贴装:NO技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

MC10117L 数据手册

 浏览型号MC10117L的Datasheet PDF文件第2页浏览型号MC10117L的Datasheet PDF文件第3页浏览型号MC10117L的Datasheet PDF文件第4页浏览型号MC10117L的Datasheet PDF文件第5页浏览型号MC10117L的Datasheet PDF文件第6页浏览型号MC10117L的Datasheet PDF文件第7页 
MC10117  
Dual 2-Wide 2-3-Input  
OR-AND/OR-AND Gate  
The MC10117 is  
a
dual 2–wide 2–3–input  
OR–AND/OR–AND–Invert gate. This general purpose logic element  
is designed for use in data control, such as digital multiplexing or data  
distribution. Pin 9 is common to both gates.  
http://onsemi.com  
P = 100 mW typ/pkg (No Load)  
D
MARKING  
DIAGRAMS  
t = 2.3 ns typ  
pd  
t , t = 2.2 ns typ (20%–80%)  
r
f
16  
CDIP–16  
L SUFFIX  
CASE 620  
LOGIC DIAGRAM  
MC10117L  
AWLYYWW  
4
5
1
3
2
16  
6
7
PDIP–16  
P SUFFIX  
CASE 648  
MC10117P  
AWLYYWW  
9
1
1
10  
11  
14  
15  
PLCC–20  
FN SUFFIX  
CASE 775  
10117  
AWLYYWW  
12  
13  
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
V
EE  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
DIP  
PIN ASSIGNMENT  
V
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
OUT  
OUT  
CC2  
ORDERING INFORMATION  
B
OUT  
A
A
Device  
Package  
Shipping  
B
OUT  
MC10117L  
CDIP–16  
25 Units / Rail  
B1  
A1  
IN  
IN  
IN  
IN  
IN  
MC10117P  
PDIP–16  
PLCC–20  
25 Units / Rail  
46 Units / Rail  
B1  
A1  
IN  
MC10117FN  
B2  
A2  
A2  
V
IN  
B2  
IN  
A2 , B2  
IN  
IN  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion Tables on page 18  
of the ON Semiconductor MECL Data Book (DL122/D).  
Semiconductor Components Industries, LLC, 2002  
1
Publication Order Number:  
January, 2002 – Rev. 7  
MC10117/D  

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