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MC100EP016AFAR2 PDF预览

MC100EP016AFAR2

更新时间： 2024-09-12 22:05:27
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路
页数 文件大小 规格书
12页 102K
描述
3.3 V ECL 8-Bit Synchronous Binary Up Counter

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MC100EP016AFAR2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP-32
针数：32Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：8.29其他特性：NECL MODE: VCC = 0V WITH VEE = -3.0V TO -3.6V
计数方向：UP系列：100E
JESD-30 代码：S-PQFP-G32JESD-609代码：e0
长度：7 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：1200000000 Hz
工作模式：SYNCHRONOUS位数：8
功能数量：1端子数量：32
最高工作温度：70 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：240电源：-4.5 V
最大电源电流（ICC）：210 mA传播延迟（tpd）：0.7 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Counters最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：ECL
温度等级：OTHER端子面层：Tin/Lead (Sn80Pb20)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
触发器类型：POSITIVE EDGE宽度：7 mm
最小 fmax：1200 MHzBase Number Matches：1

MC100EP016AFAR2 数据手册

 浏览型号MC100EP016AFAR2的Datasheet PDF文件第2页浏览型号MC100EP016AFAR2的Datasheet PDF文件第3页浏览型号MC100EP016AFAR2的Datasheet PDF文件第4页浏览型号MC100EP016AFAR2的Datasheet PDF文件第5页浏览型号MC100EP016AFAR2的Datasheet PDF文件第6页浏览型号MC100EP016AFAR2的Datasheet PDF文件第7页 
MC100EP016A  
3.3 VꢀECL 8−Bit  
Synchronous Binary  
Up Counter  
The MC100EP016A is a high−speed synchronous, presettable,  
cascadeable 8−bit binary counter. Architecture and operation are the  
same as the ECLinPS family MC100E016 with higher operating  
speed.  
http://onsemi.com  
MARKING  
The counter features internal feedback to TC gated by the TCLD  
(Terminal Count Load) pin. When TCLD is LOW (or left open, in  
which case it is pulled LOW by the internal pulldowns), the TC  
feedback is disabled, and counting proceeds continuously, with TC  
going LOW to indicate an all−one state. When TCLD is HIGH, the TC  
feedback causes the counter to automatically reload upon TC = LOW,  
thus functioning as a programmable counter. The Qn outputs do not  
need to be terminated for the count function to operate properly. To  
minimize noise and power, unused Q outputs should be left  
unterminated.  
DIAGRAM*  
LQFP−32  
FA SUFFIX  
CASE 873A  
MC100  
EP016A  
AWLYYWW  
32  
1
COUT and COUT provide differential outputs from a single,  
non−cascaded counter or divider application. COUT and COUT  
should not be used in cascade configuration. Only TC should be used  
for a counter or divider cascade chain output.  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
A differential clock input has also been added to improve  
performance.  
The 100 Series contains temperature compensation.  
*For additional information, see Application Note  
AND8002/D  
• 550 ps Typical Propagation Delay  
• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016  
ORDERING INFORMATION  
• PECL Mode Operating Range: V = 3.0 V to 3.6 V  
CC  
†
with V = 0 V  
EE  
Device  
Package  
Shipping  
• NECL Mode Operating Range: V = 0 V  
CC  
MC100EP016AFA  
LQFP−32  
250 Units/Tray  
with V = −3.0 V to −3.6 V  
EE  
MC100EP016AFAR2 LQFP−32 2000/Tape & Reel  
• Open Input Default State  
• Safety Clamp on Clock Inputs  
• Internal TC Feedback (Gated)  
• Addition of COUT and COUT  
• 8−Bit  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specifications  
Brochure, BRD8011/D.  
• Differential Clock Input  
• V Output  
BB  
• Fully Synchronous Counting and TC Generation  
• Asynchronous Master Reset  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
May 2004 − Rev. 4  
MC100EP016A/D  
1234567...12

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MC100EP016AFAR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP016AFAR2G ONSEMI

完全替代

 3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC10EP016FAR2G ONSEMI

完全替代

 3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AFA ONSEMI

完全替代

 3.3 V ECL 8-Bit Synchronous Binary Up Counter

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