Datasheet > MC100EP016A_06

MC100EP016A_06

更新时间： 2024-11-24 05:10:27

品牌	Logo	应用领域
安森美 - ONSEMI		计数器
页数	文件大小	规格书
11页	157K
描述
3.3 V ECL 8−Bit Synchronous Binary Up Counter

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MC100EP016A_06 数据手册

MC100EP016A

3.3 VꢀECL 8−Bit

Synchronous Binary

Up Counter

Description

http://onsemi.com

MARKING

The MC100EP016A is a high−speed synchronous, presettable,

cascadeable 8−bit binary counter. Architecture and operation are the

same as the ECLinPS™ family MC100E016 with higher operating

speed.

DIAGRAM*

The counter features internal feedback to TC gated by the TCLD

(Terminal Count Load) pin. When TCLD is LOW (or left open, in

which case it is pulled LOW by the internal pulldowns), the TC

feedback is disabled, and counting proceeds continuously, with TC

going LOW to indicate an all−one state. When TCLD is HIGH, the TC

feedback causes the counter to automatically reload upon TC = LOW,

thus functioning as a programmable counter. The Qn outputs do not

need to be terminated for the count function to operate properly. To

minimize noise and power, unused Q outputs should be left

unterminated.

MC100

EP016A

AWLYYWWG

LQFP−32

FA SUFFIX

CASE 873A

= Assembly Location

= Wafer Lot

= Year

COUT and COUT provide differential outputs from a single,

non−cascaded counter or divider application. COUT and COUT

should not be used in cascade configuration. Only TC should be used

for a counter or divider cascade chain output.

= Work Week

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

A differential clock input has also been added to improve

performance.

The 100 Series contains temperature compensation.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

Features

• 550 ps Typical Propagation Delay

• Operation Frequency > 1.3 GHz is 30% Faster than MC100EP016

• PECL Mode Operating Range: V = 3.0 V to 3.6 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −3.0 V to −3.6 V

• Open Input Default State

• Safety Clamp on Clock Inputs

• Internal TC Feedback (Gated)

• Addition of COUT and COUT

• 8−Bit

• Differential Clock Input

• V Output

• Fully Synchronous Counting and TC Generation

• Asynchronous Master Reset

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November 2006 − Rev. 6

MC100EP016A/D

12 3 4 5 6 7...11

中文翻译

下载PDF

与MC100EP016A_06相关器件

型号	品牌	获取价格	描述	数据表
MC100EP016AFA	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AFAG	ONSEMI	获取价格	3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AFAR2	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AFAR2G	ONSEMI	获取价格	3.3 V ECL 8−Bit Synchronous Binary Up Counter
MC100EP016AMNG	ONSEMI	获取价格	3.3 V ECL 8-Bit Synchronous Binary Up Counter
MC100EP016AMNR2G	ONSEMI	获取价格	100E SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, QCC32, 5 X 5 MM, 1 MM HE
MC100EP016AMNR4G	ONSEMI	获取价格	ECL 8 位同步二进制计数器
MC100EP016FA	ONSEMI	获取价格	3.3V / 5VECL 8-Bit Synchronous Binary Up Counter
MC100EP016FA	CHERRY	获取价格	Binary Counter, PQFP32, PLASTIC, TQFP-32
MC100EP016FAG	ONSEMI	获取价格	3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter

与MC100EP016A_06相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

39
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

31
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

59
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

55

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100EP016A_06

MC100EP016A_06 数据手册

与MC100EP016A_06相关器件

与MC100EP016A_06相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MC100EP016A_06

MC100EP016A_06 数据手册

与MC100EP016A_06相关器件

与MC100EP016A_06相关文章

您还可以找

您在本页遇到什么问题？