MC100EL34

更新时间： 2024-02-18 09:31:13

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
3页	98K
描述
±2,±4,±8 Clock Generation Chip

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MC100EL34 数据手册

SEMICONDUCTOR TECHNICAL DATA

÷ ÷ ÷

The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended ECL or, if positive power supplies are used,

PECL input signal. In addition, by using the V

source can be AC coupled into the device (see Interfacing section of the

ECLinPS Data Book DL140/D). If a single-ended input is to be used, the

output, a sinusoidal

output should be connected to the CLK input and bypassed to ground

via a 0.01µF capacitor. The V

output is designed to act as the switching

reference for the input of the EL34 under single-ended input conditions,

as a result, this pin can only source/sink up to 0.5mA of current.

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B-05

The common enable (EN) is synchronous so that the internal dividers

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

Upon startup, the internal flip-flops will attain a random state; the

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple EL34s in a system.

PIN DESCRIPTION

FUNCTION

CLK

Diff Clock Inputs

Sync Enable

Master Reset

Reference Output

Diff ÷2 Outputs

Diff ÷4 Outputs

Diff ÷8 Outputs

• 50ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• 75kΩ Internal Input Pulldown Resistors

• >1000V ESD Protection

FUNCTION TABLE

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

CLK

MR FUNCTION

CLK CLK

Divide

Hold Q

0–3

Reset Q

0–3

Z = Low-to-High Transition

ZZ = High-to-Low Transition

÷2

÷4

÷8

12/93

Motorola, Inc. 1996

REV 2

3–1

12 3

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与MC100EL34相关器件

型号	品牌	获取价格	描述	数据表
MC100EL34D	MOTOROLA	获取价格	±2, ±4, ±8 Clock Generation Chip
MC100EL34D	ONSEMI	获取价格	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC100EL34DG	ONSEMI	获取价格	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC100EL34DR2	ONSEMI	获取价格	±2,±4,±8 Clock Generation Chip
MC100EL34DR2G	ONSEMI	获取价格	5V ECL ±2, ±4, ±8 Clock Generation Chip
MC100EL35	ONSEMI	获取价格	JK Flip-Flop
MC100EL35D	MOTOROLA	获取价格	JK Flip-Flop.
MC100EL35D	ONSEMI	获取价格	5V ECL JK Flip-Flop
MC100EL35DG	ONSEMI	获取价格	5V ECL JK Flip-Flop
MC100EL35DR2	ONSEMI	获取价格	5V ECL JK Flip-Flop

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