5秒后页面跳转
MC100E137FN PDF预览

MC100E137FN

更新时间: 2024-11-22 22:30:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器触发器逻辑集成电路输出元件输入元件
页数 文件大小 规格书
5页 121K
描述
8-BIT RIPPLE COUNTER

MC100E137FN 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:QCCJ, LDCC28,.5SQReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.77
其他特性:COMPLEMENTARY OUTPUTS; DIFFERENTIAL CLOCK INPUT; ASYN/SYN COUNT ENABLE INPUT计数方向:UP
系列:100EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.5062 mm
负载/预设输入:NO逻辑集成电路类型:BINARY COUNTER
最大频率@ Nom-Sup:1800000000 Hz工作模式:ASYNCHRONOUS
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:-4.5 V
最大电源电流(ICC):167 mA传播延迟(tpd):4.95 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:Counters表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:11.5062 mm
最小 fmax:1800 MHzBase Number Matches:1

MC100E137FN 数据手册

 浏览型号MC100E137FN的Datasheet PDF文件第2页浏览型号MC100E137FN的Datasheet PDF文件第3页浏览型号MC100E137FN的Datasheet PDF文件第4页浏览型号MC100E137FN的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E137 is a very high speed binary ripple counter. The  
two least significant bits were designed with very fast edge rates while the  
more significant bits maintain standard ECLinPS output edge rates.  
This allows the counter to operate at very high frequencies while  
maintaining a moderate power dissipation level.  
1.8GHz Minimum Count Frequency  
8-BIT RIPPLE  
COUNTER  
Differential Clock Input and Data Output Pins  
V  
Output for Single-Ended Use  
BB  
Internal 75kInput Pulldown Resistors  
Synchronous and Asynchronous Enable Pins  
Asynchronous Master Reset  
Extended 100E V  
EE  
Range of –4.2V to –5.46V  
The device is ideally suited for multiple frequency clock generation as  
well as a counter in a high performance ATE time measurement board.  
Both asynchronous and synchronous enables are available to  
maximize the device’s flexibility for various applications. The  
asynchronous enable input, A_Start, when asserted enables the counter  
while overriding any synchronous enable signals. The E137 features  
XORed enable inputs, EN1 and EN2, which are synchronous to the CLK  
input. When only one synchronous enable is asserted the counter  
becomes disabled on the next CLK transition; all outputs remain in the  
previous state poised for the other synchronous enable or A_Start to be  
asserted to re-enable the counter. Asserting both synchronous enables  
causes the counter to become enabled on the next transition of the CLK.  
If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been  
inserted in the CLK path (to compensate for the XOR gate delay and the  
internal D-flip flop setup time) to insure that the synchronous enable  
signal is clocked correctly, hence, the counter is disabled.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
PIN NAMES  
PIN  
FUNCTION  
CLK, CLK  
Differential Clock Inputs  
Q0-Q7, Q0-Q7 Differential Q Outputs  
The E137 can also be driven single-endedly utilizing the V  
output  
BB  
supply as the voltage reference for the CLK input signal. If a single-ended  
signal is to be used the V pin should be connected to the CLK input and  
A_Start  
EN1, EN2  
MR  
Asynchronous Enable Input  
Synchronous Enable Inputs  
Asynchronous Master Reset  
Switching Refernce Output  
BB  
bypassed to ground via a 0.01µF capacitor. V  
can only source/sink  
BB  
V
BB  
0.5mA, therefore it should be used as a switching reference for the E137  
only.  
All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs  
open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias  
regulators and jeopardizing the stability of the device.  
The asynchronous Master Reset resets the counter to an all zero state upon assertion.  
LOGIC DIAGRAM  
A_Start  
EN1  
R
Q0 Q0  
Q1 Q1  
Q7 Q7  
D
EN2  
Q
Q
CLK  
CLK  
CLK  
CLK  
Q
Q
CLK  
CLK  
Q
Q
CLK  
CLK  
Q
Q
CLK  
CLK  
D
D
D
R
R
R
V
BB  
MR  
7/96  
Motorola, Inc. 1996  
REV 2  

与MC100E137FN相关器件

型号 品牌 获取价格 描述 数据表
MC100E137FNG ONSEMI

获取价格

5 V ECL 8-Bit Ripple Counter
MC100E137FNR2 ONSEMI

获取价格

5 V ECL 8-Bit Ripple Counter
MC100E137FNR2G ONSEMI

获取价格

5 V ECL 8-Bit Ripple Counter
MC100E141 ONSEMI

获取价格

8-BIT SHIFT REGISTER
MC100E141FN MOTOROLA

获取价格

8-BIT SHIFT REGISTER
MC100E141FN ONSEMI

获取价格

5V ECL 8-Bit Shift Register
MC100E141FNG ONSEMI

获取价格

5V ECL 8-Bit Shift Register
MC100E141FNR2 ONSEMI

获取价格

5V ECL 8-Bit Shift Register
MC100E141FNR2G ONSEMI

获取价格

5V ECL 8-Bit Shift Register
MC100E142 ONSEMI

获取价格

9-BIT SHIFT REGISTER